A 6.3-9-GHz CMOS fast settling PLL for MB-OFDM UWB applications

A CMOS phase-locked loop (PLL) which synthesizes frequencies between 6.336 and 8.976 GHz in steps of 528 MHz and settles in approximately 150 ns is presented. The proposed PLL can be employed as a building block for a frequency synthesizer which generates a seven-band hopping carrier for multiband orthogonal frequency division multiplexing (MB-OFDM) ultrawideband (UWB) radio. To achieve fast loop settling, integer-N architecture that operates with 528-MHz reference frequency is implemented and a wideband active-loop filter is integrated. An improved phase-frequency detector (PFD) is proposed for faster loop settling. To reduce reference sidebands, a feedback circuit using replica bias is implemented in the charge pump. I/Q carriers are generated by two cross-coupled LC VCOs. The output current of the charge pump is controlled to compensate for the VCO gain nonlinearity and a programmable frequency divider (12/spl les/N/spl les/17) that reliably operates at 9 GHz is designed. Fabricated in 0.18-/spl mu/m CMOS technology, the PLL consumes 32 mA from a 1.8-V supply and achieves phase noise of -109.6dBc/Hz at 1-MHz offset and spurs of -52 dBc.

[1]  E. Klumperink,et al.  Reducing MOSFET 1/f noise and power consumption by switched biasing , 1999, IEEE Journal of Solid-State Circuits.

[2]  F. Gardner,et al.  Charge-Pump Phase-Lock Loops , 1980, IEEE Trans. Commun..

[3]  Henk Jan Bergveld,et al.  A 15-mW fully integrated I/Q synthesizer for Bluetooth in 0.18-/spl mu/m CMOS , 2003 .

[4]  C.S. Vaucher,et al.  An adaptive PLL tuning system architecture combining high spectral purity and fast settling time , 2000, IEEE Journal of Solid-State Circuits.

[5]  Hyung-Kyu Lim,et al.  A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL , 1997 .

[6]  B. Razavi,et al.  A 2.6-GHz/5.2-GHz frequency synthesizer in 0.4-/spl mu/m CMOS technology , 2000, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).

[7]  A. Ismail,et al.  A 3.1 to 8.2 GHz direct conversion receiver for MB-OFDM UWB communications , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[8]  Christoph Sandner,et al.  A subpicosecond jitter PLL for clock generation in 0.12-/spl mu/m digital CMOS , 2003 .

[9]  D. Leenaerts,et al.  A SiGe BiCMOS 1ns fast hopping frequency synthesizer for UWB radio , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[10]  P.R. Gray,et al.  A 1.4 GHz differential low-noise CMOS frequency synthesizer using a wideband PLL architecture , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[11]  P. Larsson,et al.  A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capability , 1999, IEEE J. Solid State Circuits.

[12]  G.R. Aiello,et al.  Design of a multiband OFDM system for realistic UWB channel environments , 2004, IEEE Transactions on Microwave Theory and Techniques.

[13]  S. Pellerano,et al.  Phase noise in digital frequency dividers , 2004, IEEE Journal of Solid-State Circuits.

[14]  B. Razavi,et al.  A stabilization technique for phase-locked frequency synthesizers , 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).

[15]  C.-K.K. Yang,et al.  Fast frequency acquisition phase-frequency detectors for Gsamples/s phase-locked loops , 2002, IEEE J. Solid State Circuits.

[16]  M. Tiebout,et al.  Low-power low-phase-noise differentially tuned quadrature VCO design in standard CMOS , 2001, IEEE J. Solid State Circuits.

[17]  V. von Kaenel,et al.  A 4-GHz clock system for a high-performance system-on-a-chip design , 2001 .

[18]  A. Rofougaran,et al.  A 900 MHz CMOS LC-oscillator with quadrature outputs , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.