IJTAG supported 3D DFT using chiplet-footprints for testing multi-chips active interposer system

In order to increase the circuit yield, 2.5D technology have been introduced to partition a single large circuit in multiple circuits, which are tested before bonding and then assembled in 3D onto a passive silicon interposer. Active interposer is nowadays envisioned in order to provide added values within the interposer and the 3D complete system. The testability of 2.5D interposers have already been well studied but no 3D DFT have already been proposed for active interposers. In this paper, a 3D Design-for-Test architecture is proposed for testing multi-chips stacked onto an active interposer. The 3D-DFT is based on a chiplet footprint architecture, allowing the modular test of any chiplets, and is implemented using IJTAG IEEE1687 standard, offering easy test pattern retargeting from chiplet pre-bond test to the 3D circuit final test. The proposed 3D-DFT architecture and the associated 3D test flow have been fully applied onto a 3D active interposer circuit prototype and used extensively to test interposer active links, interposer passive links and all embedded memory BIST engines.

[1]  Giorgio Di Natale,et al.  2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT Architectures , 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

[2]  Mario H. Konijnenburg,et al.  A structured and scalable test access architecture for TSV-based 3D stacked ICs , 2010, 2010 28th VLSI Test Symposium (VTS).

[3]  Giorgio Di Natale,et al.  3D DFT Challenges and Solutions , 2015, 2015 IEEE Computer Society Annual Symposium on VLSI.

[4]  Giorgio Di Natale,et al.  3D Design For Test Architectures Based on IEEE P1687 , 2013 .

[5]  Qiang Xu,et al.  Test architecture design and optimization for three-dimensional SoCs , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[6]  Vivek Chickermane,et al.  A DfT Architecture and Tool Flow for 3-D SICs With Test Data Compression, Embedded Cores, and Multiple Towers , 2015, IEEE Design & Test.

[7]  E. Beyne,et al.  Active-lite interposer for 2.5 & 3D integration , 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

[8]  Xiaoxia Wu,et al.  Scan chain design for three-dimensional integrated circuits (3D ICs) , 2007, 2007 25th International Conference on Computer Design.

[9]  Hsien-Hsin S. Lee,et al.  A scanisland based design enabling prebond testability in die-stacked microprocessors , 2007, 2007 IEEE International Test Conference.