BSIM4 high-frequency model verification for 0.13 /spl mu/m RF-CMOS technology
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S.P. Voinigescu | M.T. Yang | M. Tazlauanu | P.P.C. Ho | Y.T. Chia | Y.J. Wang | T.J. Yeh | C.K. Lin | K.L. Young
[1] J.C.H. Lin,et al. State-of-the-art RF/analog foundry technology , 2002, Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting.
[2] R. Gharpurey,et al. RF MOSFET modeling accounting for distributed substrate and channel resistances with emphasis on the BSIM3v3 SPICE model , 1997, International Electron Devices Meeting. IEDM Technical Digest.
[3] C.S. Chang,et al. Extended 0.13 /spl mu/m CMOS technology for the ultra high-speed and MS/RF application segments , 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).
[4] J. Y. Cheng,et al. A 0.13 /spl mu/m CMOS technology with 193 nm lithography and Cu/low-k for high performance applications , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).