Oxidation-induced stress in Si nanopillars

[1]  T. Endoh,et al.  Edge effect in the oxidation of three-dimensional nano-structured silicon , 2019, Materials Science in Semiconductor Processing.

[2]  H. Ohno,et al.  Spin transport and spin torque in antiferromagnetic devices , 2018 .

[3]  T. Nozaki,et al.  Observation of perpendicular exchange bias in an Ir-doped Fe2O3/Co ultrathin film system. , 2017, Physical chemistry chemical physics : PCCP.

[4]  Xinhua Li,et al.  Synthesis and morphology control of diluted Si nanowire arrays by metal-assisted chemical etching and thermal oxidation based on nanosphere lithography , 2017, Journal of Materials Science.

[5]  Y. Gan,et al.  Two-dimensional modeling of the self-limiting oxidation in silicon and tungsten nanowires , 2016, 1911.08908.

[6]  Shoji Ikeda,et al.  An Overview of Nonvolatile Emerging Memories— Spintronics for Working Memories , 2016, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[7]  Youssouf Guerfi,et al.  Vertical Silicon Nanowire Field Effect Transistors with Nanoscale Gate-All-Around , 2016, Nanoscale Research Letters.

[8]  Cheng Xu,et al.  Fabricating vertically aligned sub-20 nm Si nanowire arrays by chemical etching and thermal oxidation , 2016, Nanotechnology.

[9]  T. Endoh,et al.  Low-frequency noise reduction in vertical MOSFETs having tunable threshold voltage fabricated with 60 nm CMOS technology on 300 mm wafer process , 2015 .

[10]  C. Krzeminski,et al.  Modelling and engineering of stress based controlled oxidation effects for silicon nanostructure patterning , 2013, Nanotechnology.

[11]  Zhengcao Li,et al.  The fabrication of large-scale sub-10-nm core-shell silicon nanowire arrays , 2013, Nanoscale Research Letters.

[12]  Runsheng Wang,et al.  Two-Dimensional Self-Limiting Wet Oxidation of Silicon Nanowires: Experiments and Modeling , 2013, IEEE Transactions on Electron Devices.

[13]  G. Pourtois,et al.  Self-Limiting Oxidation in Small-Diameter Si Nanowires , 2012 .

[14]  Chang Liu,et al.  Mechanical properties of Si nanowires as revealed by in situ transmission electron microscopy and molecular dynamics simulations. , 2012, Nano letters.

[15]  C. Krzeminski,et al.  Understanding of the retarded oxidation effects in silicon nanostructures , 2012, 1203.2803.

[16]  Bin Yu,et al.  Fabrication of vertically stacked single-crystalline Si nanowires using self-limiting oxidation , 2012, Nanotechnology.

[17]  Thomas Ernst,et al.  Modeling stress retarded self-limiting oxidation of suspended silicon nanowires for the development of silicon nanowire-based nanodevices , 2011 .

[18]  Julia R. Greer,et al.  Plasticity in small-sized metallic systems: Intrinsic versus extrinsic size effect , 2011 .

[19]  E. Dubois,et al.  Realization of ultra dense arrays of vertical silicon nanowires with defect free surface and perfect anisotropy using a top-down approach , 2011 .

[20]  T. Endoh,et al.  Fabrication of Silicon Pillar with 25 nm Half Pitch Using New Multiple Double Patterning Technique , 2011 .

[21]  W. Cai,et al.  Size and temperature effects on the fracture mechanisms of silicon nanowires: Molecular dynamics simulations , 2010 .

[22]  H. Ohno,et al.  A perpendicular-anisotropy CoFeB-MgO magnetic tunnel junction. , 2010, Nature materials.

[23]  Guo-Qiang Lo,et al.  Modeling of Stress-Retarded Thermal Oxidation of Nonplanar Silicon Structures for Realization of Nanoscale Devices , 2010, IEEE Electron Device Letters.

[24]  Thierry Baron,et al.  Size effects in mechanical deformation and fracture of cantilevered silicon nanowires. , 2009, Nano letters.

[25]  Shufeng Bai,et al.  Wafer-scale patterning of sub-40 nm diameter and high aspect ratio (>50:1) silicon pillar arrays by nanoimprint and etching , 2008, Nanotechnology.

[26]  G. Yang,et al.  Origin of self-limiting oxidation of Si nanowires. , 2008, Nano letters.

[27]  B. Yang,et al.  Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET , 2008, IEEE Electron Device Letters.

[28]  Takanobu Watanabe,et al.  A Kinetic Equation for Thermal Oxidation of Silicon Replacing the Deal–Grove Equation , 2007 .

[29]  X. Han,et al.  Low‐Temperature In Situ Large‐Strain Plasticity of Silicon Nanowires , 2007, Advanced Materials.

[30]  Iwao Ohdomari,et al.  Strain Distribution around SiO2/Si Interface in Si Nanowires: A Molecular Dynamics Study , 2007 .

[31]  Zhipeng Huang,et al.  Fabrication of Silicon Nanowire Arrays with Controlled Diameter, Length, and Density , 2007 .

[32]  M. Zacharias,et al.  Retarded oxidation of Si nanowires , 2006 .

[33]  Takanobu Watanabe,et al.  New linear-parabolic rate equation for thermal oxidation of silicon. , 2006, Physical review letters.

[34]  Suzanne E. Mohney,et al.  Oxidation of silicon nanowires , 2006 .

[35]  Takanobu Watanabe,et al.  SiO2/Si interface structure and its formation studied by large-scale molecular dynamics simulation , 2004 .

[36]  A. Pasquarello,et al.  Reaction of the oxygen molecule at the Si(100)-SiO2 interface during silicon oxidation. , 2004, Physical review letters.

[37]  N. Kumagai,et al.  Layer-resolved kinetics of Si oxidation investigated using the reflectance difference oscillation method , 2003 .

[38]  K. Kawamura,et al.  Technological innovation in low-dose SIMOX wafers fabricated by an internal thermal oxidation (ITOX) process , 2003 .

[39]  K. Shiraishi,et al.  Phenomenological Theory on Si Layer-by-Layer Oxidation with Small Interfacial Islands , 2000 .

[40]  T. Hattori,et al.  Structural transition layer at SiO 2 / S i interfaces , 1999 .

[41]  Kenji Shiraishi,et al.  First-Principles Study of Oxide Growth on Si(100) Surfaces and at SiO 2 /Si(100) Interfaces , 1998 .

[42]  Alfredo Pasquarello,et al.  Interface structure between silicon and its oxide by first-principles molecular dynamics , 1998, Nature.

[43]  Kiyoyuki Terakura,et al.  KINETICS OF INITIAL LAYER-BY-LAYER OXIDATION OF SI(001) SURFACES , 1998 .

[44]  Tetsuo Endoh,et al.  An Accurate Model of Fully-Depleted Surrounding Gate Transistor (FD-SGT) , 1997 .

[45]  Seiichi Miyazaki,et al.  Structure and electronic states of ultrathin SiO2 thermally grown on Si(100) and Si(111) surfaces , 1997 .

[46]  Y. Sugita,et al.  High-Density Layer at the SiO2/Si Interface Observed by Difference X-Ray Reflectivity , 1996 .

[47]  T. Hattori,et al.  Periodic changes in SiO2/Si(111) interface structures with progress of thermal oxidation , 1994 .

[48]  Roger Fabian W. Pease,et al.  Self‐limiting oxidation for fabricating sub‐5 nm silicon nanowires , 1994 .

[49]  K. Saraswat,et al.  Two-dimensional thermal oxidation of silicon—I. Experiments , 1987, IEEE Transactions on Electron Devices.

[50]  H. Z. Massoud,et al.  Silicon Oxidation Studies: Silicon Orientation Effects on Thermal Oxidation , 1986 .

[51]  R. B. Marcus,et al.  The Oxidation of Shaped Silicon Surfaces , 1982 .

[52]  Bruce E. Deal,et al.  Dependence of Interface State Density on Silicon Thermal Oxidation Process Variables , 1979 .

[53]  E. P. EerNisse,et al.  Viscous flow of thermal SiO2 , 1977 .

[54]  A. S. Grove,et al.  General Relationship for the Thermal Oxidation of Silicon , 1965 .

[55]  T. Nozaki,et al.  Inserted metals for low-energy magnetoelectric switching in a Cr2O3/ferromagnet interfacial exchange-biased thin film system , 2017 .

[56]  Robert Mertens,et al.  Thermal Oxidation of a Densely Packed Array of Vertical Si Nanowires , 2012 .

[57]  K. Yamabe,et al.  Protuberance growth at polysilicon surfaces during oxidation , 1990 .

[58]  Krishna C. Saraswat,et al.  Two-dimensional thermal oxidation of silicon. II. Modeling stress effects in wet oxides , 1988 .

[59]  James D. Plummer,et al.  Thermal oxidation of silicon in dry oxygen , 1983 .