Chip Health Tracking Using Dynamic In-Situ Delay Monitoring

Tracking the gradual effect of silicon aging requires fine-grain slack monitoring. Conventional slack monitoring techniques intend to measure worst-case static slack, i.e. the slack of longest timing path. In sharp contrast to the conventional techniques, we propose a novel technique that is based on dynamic excitation of in-situ delay monitors, i.e. dynamic excitation of the timing paths that are monitored. As the delays degrade, the path delays increase and the monitors are excited more frequently. With the proposed technique, a fine-grained signature of the delay degradation is extracted from the excitation rate of monitors.

[1]  Mark Tehranipoor,et al.  Design of Reliable SoCs With BIST Hardware and Machine Learning , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Kees G. W. Goossens,et al.  Effective In-Situ Chip Health Monitoring with Selective Monitor Insertion Along Timing Paths , 2018, ACM Great Lakes Symposium on VLSI.

[3]  Puneet Gupta,et al.  SlackProbe: A Flexible and Efficient In Situ Timing Slack Monitoring Methodology , 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Lorena Anghel,et al.  Investigation of critical path selection for in-situ monitors insertion , 2017, 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS).

[5]  Massoud Pedram,et al.  All-Region Statistical Model for Delay Variation Based on Log-Skew-Normal Distribution , 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Sorin Cotofana,et al.  Variation tolerant on-chip degradation sensors for dynamic reliability management systems , 2012, Microelectron. Reliab..

[7]  Sachin S. Sapatnekar,et al.  Estimating Circuit Aging Due to BTI and HCI Using Ring-Oscillator-Based Sensors , 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Ricardo Reis,et al.  Circuit Design for Reliability , 2014 .

[9]  Michael Nicolaidis Time redundancy based soft-error tolerance to rescue nanometer technologies , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[10]  Krishnendu Chakrabarty,et al.  Fine-Grained Aging-Induced Delay Prediction Based on the Monitoring of Run-Time Stress , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Mark Mohammad Tehranipoor,et al.  A robust digital sensor IP and sensor insertion flow for in-situ path timing slack monitoring in SoCs , 2015, 2015 IEEE 33rd VLSI Test Symposium (VTS).