A very small, flexible, high-quality, full-duplex 2.4-kbit/s linear predictive vocoder has been implemented with commercially available integrated circuits. This fully digital realization is based on a distributed signal processing architecture employing three Nippon Electric Company (NEC) pPD7720 signal processing interface (SPI) single-chip microcomputers. One SPI implements the LPC analyzer, a second implements the Gold pitch and voicing decision algorithm, while the thud pPD7720 implements the excitation generator and synthesizer. An Intel 8085-based 8-bit microcomputer is used for data transfer, control and multiplexing functions, and communications with the host terminal. The LPC chip set achieves high flexibility by accept- ing run time initialization options from the Intel 8085. These param- eters include choice of linear predictive model (< 15), analysis and synthesis frame size, and speech sampling frequency, as well as choice of speech input and output coding formats (linear or p-255 law) and choice of analog or digital pre- and deemphasis. A total of 16 inte- grated circuits is used in the LPC vocoder with a power dissipation of 5.5 W and occupying 18 in2 of circuit area.
[1]
J. Le Roux,et al.
A fixed point computation of partial correlation coefficients in linear prediction
,
1977
.
[2]
John E. Markel,et al.
Linear Prediction of Speech
,
1976,
Communication and Cybernetics.
[3]
Nick G. Kingsbury,et al.
A robust channel vocoder for adverse environments
,
1980,
ICASSP.
[4]
R. Crochiere,et al.
Speech Coding
,
1979,
IEEE Transactions on Communications.
[5]
Bernard Gold.
Computer Program for Pitch Extraction
,
1962
.
[6]
M. Leonardi,et al.
Microprocessor Implementation Of A Linear Predictive Coder
,
1979
.
[7]
Joel A. Feldman,et al.
A modular approach to packet voice terminal hardware design
,
1981,
AFIPS '81.