论文信息 - SOI-DRAM circuit technologies for low power high speed multigiga scale memories

SOI-DRAM circuit technologies for low power high speed multigiga scale memories

This paper describes a silicon on insulator (SOI) DRAM which has a body bias controlling technique for high-speed circuit operation and a new type of redundancy for low standby power operation, aimed at high yield. The body bias controlling technique contributes to super-body synchronous sensing and body-bias controlled logic. The super-body synchronous sensing achieves 3.0 ns faster sensing than body synchronous sensing and the body-bias controlled logic realizes 8.0 ns faster peripheral logic operation compared with a conventional logic scheme, at 1.5 V in a 4 Gb-level SOI DRAM. The body-bias controlled logic also realizes a body-bias change current reduction of 1/20, compared with a bulk well-structure. A new type of redundancy that overcomes the standby current failure resulting from a wordline-bitline short is also discussed in respect of yield and area penalty.

[1] Masashi Horiguchi,et al. An experimental 220 MHz 1 Gb DRAM , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

[2] Susumu Kohyama. Semiconductor technology crisis and challenges towards the year 2000 , 1994, Proceedings of 1994 VLSI Technology Symposium.

[3] Masaki Tsukude,et al. Circuit design techniques for low-voltage operating and/or giga-scale DRAMs , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

[4] John K. DeBrosse,et al. Fault-tolerant designs for 256 Mb DRAM , 1995, Digest of Technical Papers., Symposium on VLSI Circuits..

[5] Masashi Horiguchi,et al. 256-Mb DRAM circuit technologies for file applications , 1993 .

[6] Hideto Hidaka,et al. An experimental 256-Mb DRAM with boosted sense-ground scheme , 1994 .

[7] Howard Leo Kalter,et al. A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC , 1990 .

[8] M. Aoki,et al. Subthreshold current reduction for decoded-driver by self-reverse biasing (DRAMs) , 1993 .

[9] Victor E. Lee,et al. A 500-megabyte/s data-rate 4.5 M DRAM , 1993 .

[10] Hideto Hidaka,et al. An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology , 1994 .

[11] Toshiro Itani,et al. A 1-Gb DRAM for file applications , 1995 .

[12] Fukashi Morishita,et al. Leakage mechanism due to floating body and countermeasure on dynamic retention mode of SOI-DRAM , 1995, 1995 Symposium on VLSI Technology. Digest of Technical Papers.