A logic simulation machine

Special-purpose CAD hardware is increasingly being considered as a means to meet the challenge posed to conventional (software-based) CAD tools by the growing complexity of VLSI circuits. In this paper we describe the architecture of a logic simulation machine employing distributed and parallel processing. Our architecture can accommodate different levels of modeling ranging from simple gates to complex functions, and support timing analysis. We estimate that simulation implemented by the proposed special-purpose hardware will be between 10 and 60 times faster than currently used software algorithms running on general-purpose computers. With the available technology, a throughput of 1,000,000 gate evaluations/second can be achieved.

[1]  James D. Schoeffler.  Microprocessor Architecture , 1975, IEEE Transactions on Industrial Electronics and Control Instrumentation.

[2]  Ernst G. Ulrich.  Table Lookup Techniques for Fast and Flexible Digital Logic Simulation , 1980, 17th Design Automation Conference.

[3]  Howard E. Krohn.  Design verification of large scientific computers , 1977, DAC '77.

[4]  Howard E. Krohn.  Vector Coding Techniques for High Speed Digital Simulation , 1981, 18th Design Automation Conference.

[5]  J. Tellier,et al.  High-Speed Concurrent Fault Simulation with Vectors and Scalars , 1980, 17th Design Automation Conference.

[6]  Ernst G. Ulrich.  Exclusive simulation of activity in digital networks , 1969, CACM.

[7]  A. D. Friedman,et al.  Theory and Design of Switching Circuits , 1983 .

[8]  Mark Stefik,et al.  A Parallel Bit Map Processor Architecture for DA Algorithms , 1981, 18th Design Automation Conference.

[9]  Charles E. Leiserson.  Systolic Priority Queues , 1979 .

[10]  Melvin A. Breuer,et al.  Diagnosis and Reliable Design of Digital Systems , 1977 .

[11]  Michael J. Flynn,et al.  System Design of a Dynamic Microprocessor , 1970, IEEE Transactions on Computers.