A new VLSI implementation of a CMOS frequency synthesizer for SRD applications

In this paper, a new VLSI implementation of a CMOS frequency synthesizer for short range devices (SRD) applications is presented. The proposed circuit is based on PLL architecture which has a frequency divider circuit in the loop. The frequency synthesizer circuit uses a fast-acquisition PLL, which determines the improvement of the pull-in range and of the acquisition time of the circuit, providing a frequency synthesis in the range of (850–950)MHz. The CMOS frequency synthesizer proposed in the paper uses a 1MHz comparison frequency, providing the same frequency resolution. The simulations performed in a 0.13μm CMOS technology confirm the theoretical results.

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