Handling shared variable synchronization in multi-core Network-on-Chips with distributed memory
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[1] Gianluca Palermo,et al. Power/Performance Hardware Optimization for Synchronization Intensive Applications in MPSoCs , 2006, Proceedings of the Design Automation & Test in Europe Conference.
[2] Chenjie Yu,et al. Distributed and low-power synchronization architecture for embedded multiprocessors , 2008, CODES+ISSS '08.
[3] Tobias Bjerregaard,et al. A survey of research and practices of Network-on-chip , 2006, CSUR.
[4] Norman P. Jouppi,et al. Fast synchronization for chip multiprocessors , 2005, CARN.
[5] Gianluca Palermo,et al. Efficiency and scalability of barrier synchronization on NoC based many-core architectures , 2008, CASES '08.
[6] Guang R. Gao,et al. Synchronization state buffer: supporting efficient fine-grain synchronization on many-core architectures , 2007, ISCA '07.
[7] Gianluca Palermo,et al. Efficient Synchronization for Embedded On-Chip Multiprocessors , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[8] Axel Jantsch,et al. Networks on chip , 2003 .
[9] Partha Pratim Pande,et al. Performance evaluation and design trade-offs for network-on-chip interconnect architectures , 2005, IEEE Transactions on Computers.