Speeding Up Look-up-Table Driven Logic Simulation

Logic simulation is one of the most important steps in the design of a digital circuit. Due to the growing complexity of the designs, a large number of test vectors is needed, making simulation a big bottleneck. One way to speed up logic simulation is by designing distributed or parallel hardware architectures that are optimized for simulation. One such hardware accelerator is Fujitsu’s TP5000, which was shown to be over 300 times faster than a state-of-the-art software simulator on large circuits. TP5000 uses a memory-based, event-driven simulator [9]. In this paper, we propose logic restructuring techniques to further speed up functional simulation on TP5000. The key idea is to generate a perfectly balanced network logically equivalent to the original network that fits in the TP5000 memory. A perfectly balanced network gets rid of useless evaluations. We use logic decomposition, partial collapsing, and buffer insertion to generate such a network. Experimental results indicate that our techniques reduce the number of events in TP5000 by 33% as compared to a commonly-used technique that optimizes the network and does a straightforward mapping on the simulator, and by 22% as compared to the technique of [7]. On some benchmarks, the reduction is by a factor of 3.