SMTBDD: New Form of BDD for Logic Synthesis
暂无分享,去创建一个
[1] H. A. Curtis,et al. A new approach to The design of switching circuits , 1962 .
[2] Richard M. Karp,et al. Minimization Over Boolean Graphs , 1962, IBM J. Res. Dev..
[3] Dariusz Kania,et al. SMTBDD: New Concept of Graph for Function Decomposition , 2015 .
[4] Sheldon B. Akers,et al. Binary Decision Diagrams , 1978, IEEE Transactions on Computers.
[5] Randal E. Bryant,et al. Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.
[6] Adam Opara,et al. Decomposition-based logic synthesis for PAL-based CPLDs , 2010, Int. J. Appl. Math. Comput. Sci..
[7] Nagisa Ishiura,et al. Shared binary decision diagram with attributed edges for efficient Boolean function manipulation , 1990, 27th ACM/IEEE Design Automation Conference.
[8] Václav Dvorák,et al. Heuristic Synthesis of Multi-Terminal BDDs Based on Local Width/Cost Minimization , 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.
[9] Klaus Eckl,et al. A Boolean approach to performance-directed technology mapping for LUT-based FPGA designs , 1996, DAC '96.
[10] Bernd Becker,et al. The multiple variable order problem for binary decision diagrams: theory and practical application , 2001, ASP-DAC '01.
[11] Hiroshi Sawada,et al. New methods to find optimal non-disjoint bi-decompositions , 1998, Proceedings of 1998 Asia and South Pacific Design Automation Conference.
[12] Dariusz Kania,et al. Logic synthesis for PAL-based CPLD-s based on two-stage decomposition , 2007, J. Syst. Softw..
[13] Hiroyuki Ochi,et al. Breadth-first manipulation of SBDD of boolean functions for vector processing , 1991, 28th ACM/IEEE Design Automation Conference.
[14] M. Kubica,et al. Dekompozycja wielokrotna z wykorzystaniem SMTBDD , 2013 .
[15] S. Minato. Binary Decision Diagrams and Applications for VLSI CAD , 1995 .
[16] Adam Milik,et al. Logic synthesis based on decomposition for CPLDs , 2010, Microprocess. Microsystems.