Heuristic Prediction of the Optimum Number of spares in Defect-Tolerant Integrated Circuits

This paper presents a heuristic method that efficiently approximates the optimum number of spares predicted by yield models through figures of merit. This method, which is based on simple approximate functions, offers a very good trade-off between CPU time and accuracy. Indeed, the CPU time required is negligible compared to what is needed for a direct prediction of the optimum number of spares using yield models and figures of merit. Also, the approximations provided by the proposed heuristic method are very close to the exact values predicted by yield models over a wide range of parameters. A hybrid prediction method, that makes it possible to accelerate the prediction of the optimum amount of redundancy without precision losses, is also presented. This hybrid method, which uses results from the heuristic method as starting points around which yield models and figures of merit are applied, is almost optimum in terms of CPU time over the parameter range considered.