A Fault Tolerant Design Methodology for a FPGA-Based Softcore Processor

Abstract The susceptibility of digital systems to faults requires the implementation of Fault Tolerant architectures to ensure high-reliability and availability. Field Programmable Gate Arrays are especially sensitive to Single-Event Upsets and Single-Event Transients, since the configuration memory of the chip can be affected, resulting in permanent error; thus, special care must be taken when implementing Fault Tolerant architectures for FPGAs. This paper describes the architecture of a Fault Tolerant softcore processor using triplication of all units as well as using a parity protection scheme for on-chip caches, presenting the impact on area, clock frequency and I/O requirements of both implementations, targeting FPGAs. Experiments show a high fault tolerance and demonstrate the relationship of cache hit rates with fault propagation.

[1]  Ricardo Reis,et al.  Design of a robust 8-bit microprocessor to soft errors , 2006, 12th IEEE International On-Line Testing Symposium (IOLTS'06).

[2]  C. Carmichael,et al.  Proton Testing of SEU Mitigation Methods for the Virtex FPGA , 2001 .

[3]  R. Duren,et al.  Challenges of Remote FPGA Configuration for Space Applications , 2005, 2005 IEEE Aerospace Conference.

[4]  José Duato,et al.  Dealing with Transient Faults in the Interconnection Network of CMPs at the Cache Coherence Level , 2010, IEEE Transactions on Parallel and Distributed Systems.

[5]  F. Salice,et al.  Exploiting RAM for fault-tolerant functions in FPGA , 2007, 2007 2nd International Design and Test Workshop.

[6]  Jesus Lazaro,et al.  Reliable microprocessors for FPGAs: State of the art and trends , 2010, 2010 International Conference on Applied Electronics.

[7]  Fabrice Monteiro,et al.  A fault tolerant journalized stack processor architecture , 2009, 2009 15th IEEE International On-Line Testing Symposium.

[8]  Dhiraj K. Pradhan,et al.  Embedding Current Monitoring in H-Tree RAM Architecture for Multiple SEU Tolerance and Reliability Improvement , 2008, 2008 14th IEEE International On-Line Testing Symposium.

[9]  Vassilios A. Chouliaras,et al.  Study of the Effects of SEU-Induced Faults on a Pipeline Protected Microprocessor , 2007, IEEE Transactions on Computers.

[10]  Tomoyuki Ishida,et al.  A novel states recovery technique for the TMR softcore processor , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[11]  Fabio Salice,et al.  RAM-based fault tolerant state machines for FPGAs , 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

[12]  Zdenek Kotásek,et al.  Advanced fault tolerant bus for multicore system implemented in FPGA , 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

[13]  Todd M. Austin,et al.  A fault tolerant approach to microprocessor design , 2001, 2001 International Conference on Dependable Systems and Networks.

[14]  Mahdi Fazeli,et al.  Robust Register Caching: An Energy-Efficient Circuit-Level Technique to Combat Soft Errors in Embedded Processors , 2010, IEEE Transactions on Device and Materials Reliability.

[15]  C. Carmichael,et al.  A fault injection analysis of Virtex FPGA TMR design methodology , 2001, RADECS 2001. 2001 6th European Conference on Radiation and Its Effects on Components and Systems (Cat. No.01TH8605).

[16]  Adrian Thompson,et al.  Scrubbing away transients and jiggling around the permanent: long survival of FPGA systems through evolutionary self-repair , 2004, Proceedings. 10th IEEE International On-Line Testing Symposium.

[17]  R. Leveugle,et al.  A Highly Flexible Hardened RTL Processor Core Based on LEON , 2005, 2005 8th European Conference on Radiation and Its Effects on Components and Systems.

[18]  Juanjo Noguera,et al.  Fast dynamic and partial reconfiguration data path with low hardware overhead on Xilinx FPGAs , 2010, 2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW).

[19]  Jae Young Hur,et al.  A novel configuration circuit architecture to speedup reconfiguration and relocation for partially reconfigurable devices , 2010, 2010 IEEE 8th Symposium on Application Specific Processors (SASP).