We developed a new bulkstrained-Si/SiGe CMOS technology freefromanyGe-related problems, whichhasa 90-110-nm strained-Si layer thicker thanthelimit atwhich misfit-dislocations occur, anda new shallow-trench isolation structure that hasaselective-epitaxial Silayer tocover uptheSiGe trench surface. Thisprocess hasadvantages inmanufacturing compatibility withSi-CMOSprocess, lowjunction leakage current, andnoreliability problems caused byGeout-diffusion, withthe sameperformance enhancement asthin (<20un)strained-Si/SiGe.