Phase noise improvement for array systems

This paper demonstrates a phase noise improvement technique for array systems by using the phase noise filter (PNF) and the noise's uncorrelated feature. The PNF aims to suppress input signal phase noise, which is however constrained by the PNF's own circuit noise, named as the phase noise sensitivity. In array systems, the noise from each individual PNF are uncorrelated, while the input signal and noise are correlated. By leveraging this feature, the phase noise in array systems will be theoretically improved by 10×log(N), where N is the element number of the array. Both simulation and 2-element array measurement results verify this theory. In the demonstration, the phase noise of 2-element PNF array is improved to -118 dBc/Hz at 1 MHz offset for a 10 GHz clock from the single PNF's sensitivity of -116.1/-115.4 dBc/Hz, respectively. The improvement is 2-3 dB, which is very close to the theoretical value. The phase noise suppression level and input frequency range are similar to the single PNF. The demonstrated -118 dBc/Hz at 1 MHz offset for a 10 GHz clock is the best result in the CMOS process based on the authors' best knowledge.

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