Fault diagnosis system and fault diagnosis method for integrated circuit

The invention relates to a fault diagnosis system and a fault diagnosis method. The fault diagnosis method is used for diagnosing fault positions in a digital integrated circuit and comprises the following steps: step 1: establishing a fault tuple equivalent tree capable of interpreting the failure vector for each failure vector; step 2: marking the latent faults in the fault tuple equivalent tree; step 3: according to the marking results of the latent faults in the fault tuple equivalent tree, selecting the most possible fault occurrence position from each latent fault, and adding the position to the final candidate fault position set; and step 4: deleting the fault tuples which are equivalent to the faults in the final candidate fault position set or can be interpreted by the faults in the final candidate fault position set from the fault tuple equivalent tree. The system and the method of the invention can be used for diagnosing combination logic faults generating a plurality of random fault models without any area and wiring cost under the condition that new diagnosis vectors do not need to be loaded, and the traditional diagnosis processes of the combination logic faults are not changed.