Circuit-level ESD protection simulation using behavior models in 28nm CMOS

Lack of accurate ESD device models and CAD methods makes on-chip ESD protection circuit design optimization and verification impossible. This paper reports a new circuit-level ESD protection simulation method using ESD behavior models to quantitatively analyze the ESD discharging functions at chip level, including checking the transient node voltage and branch current on a chip during ESD events. The new ESD circuit simulation method is validated using ICs designed and fabricated in 28nm CMOS.

[1]  Qiong Wu,et al.  Mixed-mode ESD protection circuit simulation-design methodology , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[2]  Chen Zhang,et al.  A Systematic Study of ESD Protection Co-Design With High-Speed and High-Frequency ICs in 28 nm CMOS , 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

[3]  Tong Li,et al.  Modeling, extraction and simulation of CMOS I/O circuits under ESD stress , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[4]  Haigang Feng,et al.  ESDInspector: a new layout-level ESD protection circuitry design verification tool using a smart-parametric checking mechanism , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Junjun Li,et al.  Compact modeling of on-chip ESD protection devices using Verilog-A , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  T. Luk,et al.  Modeling MOS snapback for circuit-level ESD simulation using BSIM3 and VBIC models , 2005, Sixth international symposium on quality electronic design (isqed'05).

[7]  Chen Zhang,et al.  Concurrent Design Analysis of High-Linearity SP10T Switch With 8.5 kV ESD Protection , 2014, IEEE Journal of Solid-State Circuits.

[8]  Li Wang,et al.  Behavior modeling for whole-chip HV ESD protection circuits , 2014, 2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC's (ISPSD).

[9]  Qiong Wu,et al.  ESDExtractor: A new technology-independent CAD tool for arbitrary ESD protection device extraction , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Markus Paul Josef Mergens.  On-chip ESD protection in integrated circuits , 2001 .

[11]  Hui Zhao,et al.  Whole-chip ESD protection design verification by CAD , 2009, 2009 31st EOS/ESD Symposium.