Optimization Of Run-time Mapping On Heterogeneous CPU / FPGA Architectures

This research investigates the problem of the optimisation of run-time task mapping on a real-time computing system CPU/FPGA (Central Processing Unit/Field-Programmable Gate Array) used to implement intimately coupled hardware and software models. The case study analyzed in this work is inspired by the avionic industry. Indeed, real-time computing systems are increasingly used in aerospace and avionic industries. In the face of power wall and real-time requirements, hardware designers are directed more and more towards reconfigurable computing with the use of heterogeneous CPU/FPGA systems. In such systems, multi-core processors (CPU) provide high computation rates while the reconfigurable logic (FPGA) offers high performance and adaptability to the application real-time constraints. However, there is a lack of CAD (Computer-Aided design) tools able to deal with the development of applications on such heterogeneous systems. This work includes the development and the comparison of efficient heuristics that focus on the static initial task mapping, the dynamic mapping of new applications at run-time, and the dynamic re-configuration to avoid the real-time constraint violation.