ECO cost measurement and incremental gate sizing for late process changes

Changes in the manufacturing process parameters may create timing violations in a design, making it necessary to perform an engineering change order (ECO) to correct these problems. We present a framework for performing incremental gate sizing for process changes late in the design cycle, and a method for creating initial designs that are robust to late process changes. This includes a method for measuring and estimating ECO cost and for transforming these costs into linear programming optimization problems. In the case of ECOs, the method reduces ECO costs on average, by 89% in changed area compared to a leading commercial tool. Furthermore, the robust initial designs are, on average, 55% less likely to need redesign in the future.

[1]  David G. Chinnery,et al.  Linear programming for sizing, Vth and Vdd assignment , 2005, ISLPED '05.

[2]  Puneet Gupta,et al.  Incremental gate sizing for late process changes , 2010, 2010 IEEE International Conference on Computer Design.

[3]  Shantanu Dutt,et al.  Efficient Timing-Driven Incremental Routing for VLSI Circuits Using DFS and Localized Slack-Satisfaction Computations , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[4]  Jarrod A. Roy,et al.  ECO-system: Embracing the Change in Placement , 2007, 2007 Asia and South Pacific Design Automation Conference.

[5]  GuptaPuneet,et al.  ECO cost measurement and incremental gate sizing for late process changes , 2013 .

[6]  Yao-Wen Chang,et al.  ECO timing optimization using spare cells , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[7]  Hai Zhou,et al.  Parallel CAD: Algorithm Design and Programming Special Section Call for Papers TODAES: ACM Transactions on Design Automation of Electronic Systems , 2010 .

[8]  Yao-Wen Chang,et al.  ECO timing optimization using spare cells , 2007, ICCAD 2007.

[9]  Jarrod A. Roy,et al.  ECO-System: Embracing the Change in Placement , 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Stephen P. Boyd,et al.  Digital Circuit Optimization via Geometric Programming , 2005, Oper. Res..

[11]  Taraneh Taghavi,et al.  New placement prediction and mitigation techniques for local routing congestion , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).