An Efficient High-Power Fundamental Oscillator Above $f_{\max }/2$ : A Systematic Design

A novel approach to design efficient high-output-power fundamental oscillators beyond <inline-formula> <tex-math notation="LaTeX">$f_{\max }/2$ </tex-math></inline-formula> of the employed process is presented. The idea is to shape and maximize the unilateral power gain (<inline-formula> <tex-math notation="LaTeX">$U$ </tex-math></inline-formula>) of the network at the desired frequency using optimum passive internal and external feedback networks. The proposed technique significantly improves the output power and dc-to-RF efficiency of the oscillator. To show the feasibility of this novel approach, a 175 GHz fundamental oscillator is designed in a 130 nm SiGe BiCMOS process (<inline-formula> <tex-math notation="LaTeX">$f_{\max }\simeq ~280$ </tex-math></inline-formula> GHz), which achieves a measured dc-to-RF efficiency of 11.7% that is markedly higher than all reported oscillators above <inline-formula> <tex-math notation="LaTeX">$f_{\max }/3$ </tex-math></inline-formula> of their active device. Measurements show that the designed oscillator generates a peak power of 3 mW (4.8 dBm) with a phase noise figure of merit (FoM) of −195.4 dBc/Hz at 1 MHz offset frequency, which is the highest phase noise FoM among all reported CMOS/BiCMOS millimeter-wave and terahertz oscillators. The proposed method considers the possible process, voltage, temperature variations as well as modeling errors of the passive components in the design stage.

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