Delay considerations in testing and synthesis of integrated circuits

This dissertation studies two problems associated to delays on paths of a digital circuit. The first problem occurs in the design phase. The goal is to find an implementation for each circuit module, with appropriate area and delays on its input/output (I/O) paths, so that its performance is optimal subject to a bound on the total area. At the system or board level, the modules must also be clustered while considering expensive inter-cluster delays. In the testing phase, the goal is to generate test patterns that identify delays on paths. It is also important to be able to compare effectively the performance of different path delay fault test pattern generators on a given circuit. Time complexity analysis of all the above problems is given. Optimal polynomial time algorithms for special cases are presented which form the basis of the proposed CAD tools whose performance is tested on benchmark circuits.