A Full Adder Based on Hybrid Single-Electron Transistors and MOSFETs at Room Temperature

A full adder based on hybrid single-electron transistors (SET) and MOSFETs (SETMOS) at room temperature is proposed in this paper. Because the SET can play the same role as compensatory MOSFETs, we design a fuller adder with hybrid SETMOS. Further more, we simulate the logic element by HSPIC and the simulation result shows that the logic element implements the function of a full adder. To compare our work with conventional CMOS logics, which significantly reduces area and power consumption.

[1]  S. Mahapatra,et al.  Analytical modeling of single electron transistor for hybrid CMOS-SET analog IC design , 2004, IEEE Transactions on Electron Devices.

[2]  Chao Zhang,et al.  Nano-Reconfigurable Cells With Hybrid Circuits of Single-Electron Transistors and MOSFETs , 2010, IEEE Transactions on Electron Devices.

[3]  Anantha P. Chandrakasan,et al.  Low-power CMOS digital design , 1992 .

[4]  Ken Uchida,et al.  Programmable single-electron transistor logic for future low-power intelligent LSI: proposal and room-temperature operation , 2003 .

[5]  Hiroshi Inokawa,et al.  Experimental and simulation studies of single-electron-transistor-based multiple-valued logic , 2003, 33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings..

[6]  T. Hiramoto,et al.  Room-temperature demonstration of integrated silicon single-electron transistor circuits for current switching and analog pattern matching , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[7]  H. Inokawa,et al.  A compact analytical model for asymmetric single-electron tunneling transistors , 2003 .

[8]  Wancheng Zhang,et al.  Novel Hybrid Voltage Controlled Ring Oscillators Using Single Electron and MOS Transistors , 2007, IEEE Transactions on Nanotechnology.

[9]  Siegfried Selberherr,et al.  SIMON-A simulator for single-electron tunnel devices and circuits , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Minghua He,et al.  Reconfigurable Threshold Logic Element with SET and MOS Transistors , 2012 .

[11]  Ashok K. Goel,et al.  Design and simulation of logic circuits with hybrid architectures of single-electron transistors and conventional MOS devices at room temperature , 2008, Microelectron. J..

[12]  D. Drouin,et al.  Simulation and Design Methodology for Hybrid SET-CMOS Integrated Logic at 22-nm Room-Temperature Operation , 2012, IEEE Transactions on Electron Devices.

[13]  Jan M. Rabaey,et al.  Digital integrated circuits: a design perspective / Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic , 2003 .

[14]  Ki-Whan Song,et al.  SET/CMOS hybrid process and multiband filtering circuits , 2005 .

[15]  Yong-Bin Kim,et al.  SET-based nano-circuit simulation and design method using HSPICE , 2005, Microelectron. J..

[16]  Ioannis Karafyllidis,et al.  SECS: A New Single-Electron-Circuit Simulator , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[17]  Konstantin K. Likharev,et al.  Single-electron devices and their applications , 1999, Proc. IEEE.

[18]  Adrian M. Ionescu,et al.  Hybrid CMOS Single-Electron-Transistor Device And Circuit Design , 2006 .

[19]  Wei Wang,et al.  Hybrid Nanoelectronics: Future of Computer Technology , 2006, Journal of Computer Science and Technology.

[20]  Kaustav Banerjee,et al.  Few electron devices: towards hybrid CMOS-SET integrated circuits , 2002, DAC '02.

[21]  Yasuo Takahashi,et al.  A multiple-valued logic and memory with combined single-electron and metal-oxide-semiconductor transistors , 2003 .