Correction-Free Multi-Bit Sigma-Delta Modulators for ADSL

This chapter first presents a scalable MASH dual-quantization architecture and a companion optimum set of scaling coefficients which result into minimum resolution losses. The chapter then outlines the dominant circuit imperfections that degrade the operation of this architecture, and presents illustrative design exploration considerations induced by these circuit imperfections. Finally, some practical considerations pertaining to the implementation of an ADSL sigma-delta modulator in 0.25-μm CMOS technology are given and illustrated through experimental results.

[1]  W. Sansen,et al.  A 3.3 V 15-bit delta-sigma ADC with a signal bandwidth of 1.1 MHz for ADSL-applications , 1999, Proceedings of the 24th European Solid-State Circuits Conference.

[2]  Ángel Benito Rodríguez Vázquez,et al.  A 13-bit, 2.2-MS/s, 55-mW multibit cascade ΣΔ modulator in CMOS 0.7-μm single-poly technology , 1999 .

[3]  I. Dedic,et al.  A sixth-order triple-loop sigma-delta CMOS ADC with 90 dB SNR and 100 kHz bandwidth , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[4]  Terri S. Fiez,et al.  A Nyquist-rate delta-sigma A/D converter , 1998 .

[5]  Todd L. Brooks,et al.  A cascaded sigma-delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR , 1997 .

[6]  F. O. Eynde,et al.  A high-speed CMOS comparator with 8-b resolution , 1992 .

[7]  B. Leung,et al.  Distortion analysis of MOS track-and-hold sampling mixers using time-varying Volterra series , 1999 .

[8]  A. R. Feldman,et al.  A 13-bit, 1.4-MS/s sigma-delta modulator for RF baseband channel applications , 1998 .

[9]  W. Sansen,et al.  A high-performance multibit /spl Delta//spl Sigma/ CMOS ADC , 2000, IEEE Journal of Solid-State Circuits.

[10]  R. Schreier,et al.  Delta-sigma data converters : theory, design, and simulation , 1997 .

[11]  Atsushi Iwata,et al.  A 16-bit oversampling A-to-D conversion technology using triple-integration noise shaping , 1987 .

[12]  N. Tan,et al.  Fourth-order two-stage delta-sigma modulator using both 1 bit and multibit quantisers , 1993 .

[13]  Feng Chen,et al.  A High Resolution Multibit Sigma-Delta Modulator with Individual Level Averaging(Special Issue on the 1994 VLSI Circuits Symposium) , 1995 .

[14]  B. Hallgren Design of a Second Order CMOS Sigma-Delta A/D Converter with a 150 MHz Clock Rate , 1992, ESSCIRC '92: Eighteenth European Solid-State Circuits conference.

[15]  Ángel Rodríguez-Vázquez,et al.  Top-Down Design of High-Performance Sigma-Delta Modulators , 1998 .

[16]  V. Liberali,et al.  Cascade pseudomultibit noise shaping modulators , 1993 .

[17]  Gabor C. Temes,et al.  Digitally corrected multi-bit Sigma Delta data converters , 1989, IEEE International Symposium on Circuits and Systems,.

[18]  Bruce A. Wooley,et al.  A 50-MHz multibit sigma-delta modulator for 12-b 2-MHz A/D conversion , 1991 .

[19]  Belén Pérez-Verdú,et al.  Reliable analysis of settling errors in SC integrators: application to ΣΔ modulators , 2000 .

[20]  L. Longo,et al.  A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8/spl times/ oversampling ratio , 2000, IEEE Journal of Solid-State Circuits.

[21]  Rocío del Río,et al.  High-performance sigma-delta ADC for ADSL applications in 0.35 /spl mu/m CMOS digital technology , 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

[22]  Belén Pérez-Verdú,et al.  Multi-bit cascade /spl Sigma//spl Delta/ modulator for high-speed A/D conversion with reduced sensitivity to DAC errors , 1998 .

[23]  Belén Pérez-Verdú,et al.  A 13-bit, 2.2-MS/s, 55-mW multibit cascade /spl Sigma//spl Delta/ modulator in CMOS 0.7-/spl mu/m single-poly technology , 1999 .

[24]  R. T. Baird,et al.  A low oversampling ratio 14-b 500-kHz /spl Delta//spl Sigma/ ADC with a self-calibrated multibit DAC , 1996 .

[25]  Bosco Leung,et al.  High-order single-stage single-bit oversampling A/D converter stabilized with local feedback loops , 1994 .

[26]  W. Sansen,et al.  A 15-b resolution 2-MHz Nyquist rate /spl Delta//spl Sigma/ ADC in a 1-/spl mu/m CMOS technology , 1998 .

[27]  H. J. Casier Requirements for embedded data converters in an ADSL communication system , 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

[28]  W. Sansen,et al.  A 16-b 320-kHz CMOS A/D converter using two-stage third-order Sigma Delta noise shaping , 1993 .

[29]  T. Miki,et al.  14-bit 2.2-MS/s sigma-delta ADC's , 2000, IEEE Journal of Solid-State Circuits.

[30]  G. Temes Delta-sigma data converters , 1994 .

[31]  Willy Sansen,et al.  Analog interfaces for digital signal processing systems , 1993, The Kluwer international series in engineering and computer science.

[32]  Tai-Haur Kuo,et al.  A wideband CMOS sigma-delta modulator with incremental data weighted averaging , 2002 .

[33]  Gabor C. Temes,et al.  A high-resolution multibit Sigma Delta ADC with digital correction and relaxed amplifier requirements , 1993 .

[34]  Chuan Yi Tang,et al.  A 2.|E|-Bit Distributed Algorithm for the Directed Euler Trail Problem , 1993, Inf. Process. Lett..