A NEW DESIGN OF ALL DIGITAL PHASE-LOCKED LOOP

A new design method of a all digital phase-locked loop (DPLL)is presented. The new DPLL controller is realized by a proportional-integral method rather than by conventional loop filters. A mathematic model for the DPLL is built with the method of linear approximation, and the local dynamic characteristics are developed. It is indicated by the theoretic analysis that the new design has wide lock-in range and has same stability behavior in the neigbourhood of the locked frequency. Besides, the frequency tracking time of the DPLL is directly proportional to the period of the locked signal. Utilizing the phase error indicated by the pulse width of phase detector outputs and employing the integral control improve the capture speed. The results obtained from simulation experiments confirm the conclusions of the theoretic analysis. Since the DPLL can be realized by digital circuits and can be regulated through the proportional and integral parameters, it is easy to be designed and be used in the fields of speed governing system of motor, active power filter and static var compensator.