论文信息 - Fault tolerant architectures for efficient realization of common DSP kernels

Fault tolerant architectures for efficient realization of common DSP kernels

The authors propose combining traditional fault tolerant computer concepts with the inherent modularity of residue number system (RNS) arithmetic to provide failure resistance in high speed digital signal processing (DSP) systems. Triple modular redundancy and quadruple modular redundancy, both of which are used in commercial fault tolerant computers are combined with RNS modularity for realizing important DSP computational kernels. The combination of system level modularity and arithmetic level modularity offers a great deal of flexibility in designing efficient fault tolerant DSP kernels.<<ETX>>

W. K. Jenkins | B. A. Schnaufer

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