Adding instruction cache effect to schedulability analysis of preemptive real-time systems

Cache memories are commonly avoided in real time systems because of their unpredictable behavior. Recently, some research has been done to obtain tighter bounds on the worst case execution time (WCET) of cached programs. These techniques usually assume a non preemptive underlying system. However, some techniques can be applied to allow the use of caches in preemptive systems. The paper describes how to incorporate the effect of instruction cache to the Response Time schedulability Analysis (RTA). RTA is an efficient analysis for preemptive fixed priority schedulers. We also compare through simulations the results of such an approach to both cache partitioning (increase of the cache predictability by assigning private cache partitions to tasks) and CRMA (Cached RMA: cache effect is incorporated in the utilization based rate monotonic schedulability analysis). The results show that the cached version of RTA (CRTA) clearly outperforms CRMA, however the partitioning scheme may be better depending on the system configuration. The obtained results bound the applicability domain for each method for a variety of hardware and workload configurations. The results can be used as design guidelines.

[1]  C. Douglas Locke,et al.  Building a predictable avionics platform in Ada: a case study , 1991, [1991] Proceedings Twelfth Real-Time Systems Symposium.

[2]  David B. Whalley,et al.  Bounding worst-case instruction cache performance , 1994, 1994 Proceedings Real-Time Systems Symposium.

[3]  Andy J. Wellings,et al.  Adding instruction cache effect to an exact schedulability analysis of preemptive real-time systems , 1996, Proceedings of the Eighth Euromicro Workshop on Real-Time Systems.

[4]  Alan Jay Smith,et al.  Line (Block) Size Choice for CPU Cache Memories , 1987, IEEE Transactions on Computers.

[5]  D. B. Kirk,et al.  SMART (strategic memory allocation for real-time) cache design , 1989, [1989] Proceedings. Real-Time Systems Symposium.

[6]  Alan Jay Smith,et al.  Evaluating Associativity in CPU Caches , 1989, IEEE Trans. Computers.

[7]  John A. Stankovic,et al.  Predictable Real-Time Caching in the Spring System , 1991 .

[8]  Andrew Wolfe,et al.  Software-based cache partitioning for real-time applications , 1994 .

[9]  Mark Horowitz,et al.  Performance tradeoffs in cache design , 1988, ISCA '88.

[10]  Kuninori Kimotsuki,et al.  THE KEY-NOTE , 1991 .

[11]  Mark Horowitz,et al.  An analytical cache model , 1989, TOCS.

[12]  Laxmi N. Bhuyan,et al.  High-performance computer architecture , 1995, Future Gener. Comput. Syst..

[13]  Ray Jain,et al.  The art of computer systems performance analysis - techniques for experimental design, measurement, simulation, and modeling , 1991, Wiley professional computing.

[14]  Alan Burns,et al.  Preemptive priority-based scheduling: an appropriate engineering approach , 1995 .

[15]  Sang Lyul Min,et al.  An accurate worst case timing analysis technique for RISC processors , 1994, 1994 Proceedings Real-Time Systems Symposium.

[16]  Mark Horowitz,et al.  Cache performance of operating system and multiprogramming workloads , 1988, TOCS.

[17]  Dominique Thiébaut,et al.  On the Fractal Dimension of Computer Programs and its Application to the Prediction of the Cache Miss Ratio , 1989, IEEE Trans. Computers.

[18]  Lui Sha,et al.  Priority Inheritance Protocols: An Approach to Real-Time Synchronization , 1990, IEEE Trans. Computers.

[19]  Jyh-Charn Liu,et al.  Deterministic upperbounds of the worst-case execution times of cached programs , 1994, 1994 Proceedings Real-Time Systems Symposium.

[20]  Frank Mueller.  Compiler support for software-based cache partitioning , 1995 .

[21]  J. Leung,et al.  A Note on Preemptive Scheduling of Periodic, Real-Time Tasks , 1980, Inf. Process. Lett..

[22]  Jay K. Strosnider,et al.  Allocating SMART cache segments for schedulability , 1991 .

[23]  David B. Kirk,et al.  Process dependent static cache partitioning for real-time systems , 1988, Proceedings. Real-Time Systems Symposium.

[24]  Lee Higbee.  Quick and easy cache performance analysis , 1990, CARN.

[25]  Jay K. Strosnider,et al.  Allocating SMART cache segments for schedulability , 1991, Proceedings. EUROMICRO `91 Workshop on Real-Time Systems.

[26]  Chung Laung Liu,et al.  Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment , 1989, JACM.

[27]  Alan Burns,et al.  The Olympus Attitude and Orbital Control System: A Case Study in Hard Real-Time System Design and Implementation , 1993, Ada-Europe.

[28]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[29]  Harold S. Stone,et al.  Footprints in the cache , 1987, TOCS.

[30]  Harold S. Stone,et al.  Footprints in the cache , 1986, SIGMETRICS '86/PERFORMANCE '86.

[31]  Paul K. Harter.  Response times in level-structured systems , 1987 .

[32]  Jeffrey C. Mogul,et al.  The effect of context switches on cache performance , 1991, ASPLOS IV.

[33]  Lui Sha,et al.  Real-time scheduling theory and Ada , 1990, Computer.

[34]  Russell W. Quong.  Expected I-cache miss rates via the gap model , 1994, ISCA '94.

[35]  Kelvin D. Nilsen,et al.  Cache Issues in Real-Time Systems , 1994 .

[36]  Kelvin D. Nilsen.  Real-time is no longer a small specialized niche , 1995, Proceedings 5th Workshop on Hot Topics in Operating Systems (HotOS-V).

[37]  Mathai Joseph,et al.  Finding Response Times in a Real-Time System , 1986, Comput. J..

[38]  Jay K. Strosnider,et al.  SMART (strategic memory allocation for real-time) cache design using the MIPS R3000 , 1990, [1990] Proceedings 11th Real-Time Systems Symposium.

[39]  Lui Sha,et al.  An Optimal Priority Inheritance Protocol for Real-Time Synchronization , 1988 .

[40]  Alan Burns,et al.  STRESS: A simulator for hard real‐time systems , 1994, Softw. Pract. Exp..

[41]  Ann Marie Grizzaffi Maynard,et al.  Contrasting characteristics and cache performance of technical and multi-user commercial workloads , 1994, ASPLOS VI.