A low-power, high-performance, 1024-point FFT processor
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[1] P. A. Ruetz,et al. A real time FFT chip set: architectural issues , 1990, [1990] Proceedings. 10th International Conference on Pattern Recognition.
[2] C. Joanblanq,et al. A fast single-chip implementation of 8192 complex point FFT , 1995 .
[3] B.M. Baas. An energy-efficient single-chip FFT processor , 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.
[4] Surendar S. Magar,et al. An application specific DSP chip set for 100 MHz data rates , 1988, ICASSP-88., International Conference on Acoustics, Speech, and Signal Processing.
[5] Bevan M. Baas,et al. An approach to low-power, high-performance, Fast Fourier Transform processor design , 1999 .
[6] Alan V. Oppenheim,et al. Discrete-time Signal Processing. Vol.2 , 2001 .
[7] R. Singleton,et al. A method for computing the fast Fourier transform with auxiliary memory and limited high-speed storage , 1967, IEEE Transactions on Audio and Electroacoustics.
[8] M. Horowitz,et al. Low-power digital design , 1994, Proceedings of 1994 IEEE Symposium on Low Power Electronics.
[9] J. O'Brien,et al. A 200 MIPS single-chip 1 k FFT processor , 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.
[10] W. M. Gentleman,et al. Fast Fourier Transforms: for fun and profit , 1966, AFIPS '66 (Fall).
[11] G. Troster,et al. A high precision 1024-point FFT processor for 2D convolution , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).
[12] Bevan M. Baas,et al. Stanford's ultra-low-power CMOS technology and applications , 1996 .
[13] J. Shott,et al. A 200 mV self-testing encoder/decoder using Stanford ultra-low-power CMOS , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.
[14] Neil Weste,et al. Principles of CMOS VLSI Design , 1985 .
[15] David A. Patterson,et al. Computer Architecture: A Quantitative Approach , 1969 .
[16] C. K. Yuen,et al. Theory and Application of Digital Signal Processing , 1978, IEEE Transactions on Systems, Man, and Cybernetics.
[17] N. Brenner. Fast Fourier transform of externally stored data , 1969 .
[18] Shousheng He,et al. Design and implementation of a 1024-point pipeline FFT processor , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).
[19] David A. Patterson,et al. Computer Architecture - A Quantitative Approach, 5th Edition , 1996 .
[20] Anantha P. Chandrakasan,et al. Low-power CMOS digital design , 1992 .
[21] David H. Bailey,et al. FFTs in external or hierarchical memory , 1989, Proceedings of the 1989 ACM/IEEE Conference on Supercomputing (Supercomputing '89).
[22] J. Burr,et al. Ultra low power CMOS technology , 1991 .
[23] Tom Chen,et al. COBRA: an 1.2 million transistor expandable column FFT chip , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.