The Development of Embedded DRAM Statistical Quality Models at Test and Use Conditions

Today, the use of embedded Dynamic Random Access Memory (eDRAM) is increasing in our electronics that require large memories, such as gaming consoles and computer network routers. Unlike external DRAMs, eDRAMs are embedded inside ASICs for faster read and write operations. Until recently, eDRAMs required high manufacturing cost. Present process technology developments enabled the manufacturing of eDRAM at competitive costs. Unlike SRAM, eDRAM exhibits retention time bit fails from defects and capacitor leakage current. This retention time fail causes memory bits to lose stored values before refresh. Also, a small portion of the memory bits are known to fail at a random retention time. At test conditions, more stringent than use conditions, if all possible retention time fail bits are detected and replaced, there will be no additional fail bits during use. However, detecting all the retention time fails requires long time and also rejects bits that do not fail at the use condition. This research seeks to maximize the detection of eDRAM fail bits during test by determining effective test conditions and model the failure rate of eDRAM retention time during use conditions.