Ternary content-addressable memory with MoS2 transistors for massively parallel data search

Ternary content-addressable memory (TCAM) is specialized hardware that can perform in-memory search and pattern matching for data-intensive applications. However, achieving TCAMs with high search capacity, good area efficiency and good energy efficiency remains a challenge. Here, we show that two-transistor–two-resistor (2T2R) transition metal dichalcogenide TCAM (TMD-TCAM) cells can be created by integrating single-layer MoS2 transistors with metal-oxide resistive random-access memories (RRAMs). The MoS2 transistors have very low leakage currents and can program the RRAMs with exceptionally robust current control, enabling the parallel search of very large numbers of data bits. These TCAM cells also exhibit remarkably large resistance ratios (R-ratios) of up to 8.5 × 105 between match and mismatch states. This R-ratio is comparable to that of commercial TCAMs using static random-access memories (SRAMs), with the key advantage that our 2T2R TCAMs use far fewer transistors and have zero standby power due to the non-volatility of RRAMs.By integrating two-dimensional MoS2 transistors with metal-oxide resistive random-access memories, two-transistor–two-resistor ternary content-addressable memory cells can be created, which could be used to search large amounts of data in parallel.

[1]  Zhiping Yu,et al.  Stable self-compliance resistive switching in AlOδ/Ta2O(5-x)/TaOy triple layer devices. , 2015, Nanotechnology.

[2]  S. Koester,et al.  Dynamic Memory Cells Using MoS2 Field-Effect Transistors Demonstrating Femtoampere Leakage Currents. , 2016, ACS nano.

[3]  Shun Xu,et al.  Demonstrate high Roff/Ron ratio and forming-free RRAM for rFPGA application based on switching layer engineering , 2017, 2017 IEEE 12th International Conference on ASIC (ASICON).

[4]  Lei Wang,et al.  Multi-terminal transport measurements of MoS2 using a van der Waals heterostructure device platform. , 2015, Nature nanotechnology.

[5]  Moon J. Kim,et al.  MoS2 transistors with 1-nanometer gate lengths , 2016, Science.

[6]  P. Ye,et al.  Channel length scaling of MoS2 MOSFETs. , 2012, ACS nano.

[7]  Yu Cao,et al.  New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation , 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

[8]  G. Ghibaudo,et al.  Understanding RRAM endurance, retention and window margin trade-off using experimental results and simulations , 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

[9]  Igor Arsovski,et al.  A 32 nm 0.58-fJ/Bit/Search 1-GHz Ternary Content Addressable Memory Compiler Using Silicon-Aware Early-Predict Late-Correct Sensing With Embedded Deep-Trench Capacitor Noise Mitigation , 2013, IEEE Journal of Solid-State Circuits.

[10]  Eric Pop,et al.  Approaching ballistic transport in monolayer MoS2 transistors with self-aligned 10 nm top gates , 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

[11]  H.-S. Philip Wong,et al.  Resistive RAM-Centric Computing: Design and Modeling Methodology , 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.

[12]  Kunle Olukotun,et al.  Energy-Efficient Abundant-Data Computing: The N3XT 1,000x , 2015, Computer.

[13]  Jörg Henkel.  Emerging Memory Technologies , 2017, IEEE Des. Test.

[14]  Peilin Song,et al.  1Mb 0.41 µm2 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing , 2013, 2013 Symposium on VLSI Circuits.

[15]  K. Alam,et al.  Monolayer $\hbox{MoS}_{2}$ Transistors Beyond the Technology Road Map , 2012, IEEE Transactions on Electron Devices.

[16]  Eric Pop,et al.  Improved Contacts to MoS2 Transistors by Ultra-High Vacuum Metal Deposition. , 2016, Nano letters.

[17]  Jing Guo,et al.  On Monolayer ${\rm MoS}_{2}$ Field-Effect Transistors at the Scaling Limit , 2013, IEEE Transactions on Electron Devices.

[18]  Tetsuo Endoh,et al.  Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme , 2014, IEICE Electron. Express.

[19]  Eby G. Friedman,et al.  Resistive Ternary Content Addressable Memory Systems for Data-Intensive Computing , 2015, IEEE Micro.

[20]  Sung-Mo Steve Kang,et al.  Memristor-based ternary content addressable memory (mTCAM) for data-intensive computing , 2014 .

[21]  Tajana Simunic,et al.  Resistive configurable associative memory for approximate computing , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[22]  Wei Liu,et al.  2D Semiconductor FETs—Projections and Design for Sub-10 nm VLSI , 2015, IEEE Transactions on Electron Devices.

[23]  Vincent Anthony Mabert,et al.  Tutorial and Survey , 1972 .

[24]  Thomas N. Theis,et al.  The End of Moore's Law: A New Beginning for Information Technology , 2017, Computing in Science & Engineering.

[25]  Ole Bethge,et al.  A microprocessor based on a two-dimensional semiconductor , 2016, Nature Communications.

[26]  Kyeongjae Cho,et al.  Monolayer MoS2 Bandgap Modulation by Dielectric Environments and Tunable Bandgap Transistors , 2016, Scientific Reports.

[27]  O. Richard,et al.  10×10nm2 Hf/HfOx crossbar resistive RAM with excellent performance, reliability and low-energy operation , 2011, 2011 International Electron Devices Meeting.

[28]  L. Goux,et al.  On the Gradual Unipolar and Bipolar Resistive Switching of TiN\ HfO2\Pt Memory Systems , 2010 .

[29]  Meng-Fan Chang,et al.  17.5 A 3T1R nonvolatile TCAM using MLC ReRAM with Sub-1ns search time , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[30]  Massimiliano Di Ventra,et al.  The parallel approach , 2013 .

[31]  Shoji Ikeda,et al.  A 3.14 um2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture , 2012, 2012 Symposium on VLSI Circuits (VLSIC).

[32]  J. Kong,et al.  Large-scale 2D electronics based on single-layer MoS2 grown by chemical vapor deposition , 2012, 2012 International Electron Devices Meeting.

[33]  Towards intrinsic charge transport in monolayer molybdenum disulfide by defect and interface engineering. , 2014, Nature communications.

[34]  Igor Arsovski,et al.  Low-noise embedded CAM with reduced slew-rate match-lines and asynchronous search-lines , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

[35]  Myungsoo Kim,et al.  Atomristor: Nonvolatile Resistance Switching in Atomic Sheets of Transition Metal Dichalcogenides. , 2018, Nano letters.

[36]  Hua Zhang,et al.  Two-dimensional semiconductors for transistors , 2016 .

[37]  Meng-Fan Chang,et al.  A 3T1R Nonvolatile TCAM Using MLC ReRAM for Frequent-Off Instant-On Filters in IoT and Big-Data Processing , 2017, IEEE Journal of Solid-State Circuits.

[38]  Eric Pop,et al.  Low Variability in Synthetic Monolayer MoS2 Devices. , 2017, ACS nano.

[39]  H-S Philip Wong,et al.  Memory leads the way to better computing. , 2015, Nature nanotechnology.

[40]  H. Hwang,et al.  Improved endurance of RRAM by optimizing reset bias scheme in 1T1R configuration to suppress reset breakdown , 2016, IEEE Silicon Nanoelectronics Workshop.

[41]  E. Pop,et al.  Intrinsic electrical transport and performance projections of synthetic monolayer MoS2 devices , 2016, 1608.00987.

[42]  D. Frank,et al.  Generalized scale length for two-dimensional effects in MOSFETs , 1998, IEEE Electron Device Letters.

[43]  Rui Yang,et al.  Electrical breakdown of multilayer MoS2 field-effect transistors with thickness-dependent mobility. , 2014, Nanoscale.

[44]  Shimeng Yu,et al.  HfOx-based vertical resistive switching random access memory suitable for bit-cost-effective three-dimensional cross-point architecture. , 2013, ACS nano.

[45]  H.-S. Philip Wong,et al.  In-memory computing with resistive switching devices , 2018, Nature Electronics.

[46]  Jing Li,et al.  1 Mb 0.41 µm² 2T-2R Cell Nonvolatile TCAM With Two-Bit Encoding and Clocked Self-Referenced Sensing , 2014, IEEE Journal of Solid-State Circuits.

[47]  Shimeng Yu,et al.  Metal–Oxide RRAM , 2012, Proceedings of the IEEE.

[48]  Kinam Kim,et al.  A fast, high-endurance and scalable non-volatile memory device made from asymmetric Ta2O(5-x)/TaO(2-x) bilayer structures. , 2011, Nature materials.

[49]  Peng Huang,et al.  Device and Circuit Interaction Analysis of Stochastic Behaviors in Cross-Point RRAM Arrays , 2016, IEEE Transactions on Electron Devices.

[50]  Eric Pop,et al.  2D molybdenum disulfide (MoS2) transistors driving RRAMs with 1T1R configuration , 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

[51]  K. Pagiamtzis,et al.  Content-addressable memory (CAM) circuits and architectures: a tutorial and survey , 2006, IEEE Journal of Solid-State Circuits.

[52]  Andrew T. S. Wee,et al.  Bandgap tunability at single-layer molybdenum disulphide grain boundaries , 2015, Nature Communications.

[53]  Shanshan Yao,et al.  Surface-energy-assisted perfect transfer of centimeter-scale monolayer and few-layer MoS₂ films onto arbitrary substrates. , 2014, ACS nano.

[54]  Eric Pop,et al.  Improved Hysteresis and Reliability of MoS2 Transistors With High-Quality CVD Growth and Al2O3 Encapsulation , 2017, IEEE Electron Device Letters.