Advanced wiring RC delay issues for sub-0.25-micron generation CMOS

Measured and modeled back-end-of-the-line (BEOL) RC delay data are presented for multilevel sub-0.25 /spl mu/m generation CMOS ICs. The aluminum and copper BEOL levels were fabricated using metal RIE and damascene processing, respectively. Aluminum BEOL RC variability increases with increasing line height and is primarily caused by within-wafer intermetal dielectric (IMD) CMP removal variation and wafer-to-wafer variation in the printed and etched metal linewidths. Copper BEOL RC variability decreases with increasing line height and is dominated by metal CMP variation for thin lines and by metal trough IMD RIE depth and width tolerances for thick lines. In addition to having 40% lower sheet resistance, copper also has lower BEOL RC variability than aluminum and offers more design flexibility for BEOL RC delay and crosstalk noise optimization.