Soft connections: Addressing the hardware-design modularity problem

Hardware-design languages typically impose a rigid communication hierarchy that follows module instantiation. This leads to an undesirable side-effect where changes to a child's interface result in changes to the parents. Soft connections address this problem by allowing the user to specify connection endpoints that are automatically connected at compilation time, rather than by the user.

[1]  Arvind,et al.  Quick Performance Models Quickly: Closely-Coupled Partitioned Simulation on FPGAs , 2008, ISPASS 2008 - IEEE International Symposium on Performance Analysis of Systems and software.

[2]  Arvind,et al.  Modular scheduling of guarded atomic actions , 2004, Proceedings. 41st Design Automation Conference, 2004..

[3]  Arvind,et al.  A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs , 2008, FPGA '08.

[4]  Christoforos E. Kozyrakis,et al.  RAMP: Research Accelerator for Multiple Processors , 2007, IEEE Micro.

[5]  Babak Falsafi,et al.  A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs , 2008, FPGA '08.

[6]  Dam Sunwoo,et al.  The FAST methodology for high-speed SoC/computer simulation , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[7]  Dam Sunwoo,et al.  FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators , 2007, MICRO.