Design for a recursive parallel multiplier

A network for performing multiplications of two two's complement numbers is proposed. The network can be implemented in a synchronous or an asynchronous way. If the factors to be multiplied have N bits, the area complexity of the network is O(N2) for practical values of N as in the case of cellular multipliers. Due to the design approach based on a recursive algorithm, a time complexity O(log N) is achieved.

[1]  Christopher S. Wallace,et al.  A Suggestion for a Fast Multiplier , 1964, IEEE Trans. Electron. Comput..

[2]  R. Mori.  Suggestion for an i.c. fast parallel multiplier , 1969 .

[3]  R. De Mori,et al.  A Parallel Structure for Signed-Number Multiplication and Addition , 1972, IEEE Transactions on Computers.

[4]  A. K. Choudhury,et al.  An Iterative Array for Multiplication of Signed Binary Numbers , 1972, IEEE Transactions on Computers.

[5]  Huey Ling.  High-Speed Computer Multiplication Using a Multiple-Bit Decoding Algorithm , 1970, IEEE Transactions on Computers.

[6]  Earl E. Swartzlander,et al.  Computer Arithmetic , 1980 .

[7]  William I. Fletcher.  Engineering approach to digital design , 1980 .

[8]  I. D. Deegan.  Cellular multiplier for signed binary numbers , 1971 .

[9]  Jayanti C. Majithia,et al.  An Iterative Array for Multiplication of Signed Binary Numbers , 1971, IEEE Transactions on Computers.

[10]  H. H. Guild.  Fully iterative fast array for binary multiplication and addition , 1969 .

[11]  Bruce A. Wooley,et al.  A Two's Complement Parallel Array Multiplication Algorithm , 1973, IEEE Transactions on Computers.

[12]  Franco P. Preparata,et al.  A Mesh-Connected Area-Time Optimal VLSI Multiplier of Large Integers , 1983, IEEE Transactions on Computers.

[13]  Nick Kingsbury,et al.  High-speed binary multiplier , 1971 .

[14]  Paul A. Wintz,et al.  Fast Multipliers , 1970, IEEE Transactions on Computers.

[15]  Shanker Singh,et al.  Multiple Operand Addition and Multiplication , 1899, IEEE Transactions on Computers.

[16]  K. J. Dean.  Cellular multiplier subarrays: a critical-path approach to propagation times , 1971 .

[17]  William J. Kubitz,et al.  A Compact High-Speed Parallel Multiplication Scheme , 1977, IEEE Transactions on Computers.