Data and Commands Communication Protocol for Neuromorphic Platform Configuration

In this paper, we present a new network protocol and methodology to enhance the configuration phase of the SpiNNaker spiking neural network hardware simulator. We have developed a system able to accept and process on-board a set of configuration primitives (data specification) encapsulated into ad-hoc packets, avoiding the management of chip memory from the host computer. We performed a study of the data specification generator implemented in the host software library. Afterwards, we extended the currently on-board data specification executor to cope with the newly-formed packets. The use of UDP protocol presents challenges due to its intrinsic unreliability. Furthermore, the presence of a single Ethernet link per board, and the requirement for a dedicated processor to handle all Ethernet communications limit the available communication bandwidth. A set of simulations was performed in order to tune the protocol parameters and to study the trade-offs between transmission speed and reliability. We were able to reach a throughput of a packet every 250 μs, which corresponds to a bandwidth of ~10 Mb/s. This system is able to open new perspectives for the SpiNNaker architecture. Thus, including the reduction of the time required to configure a simulation, the ability to configure more instances of a simulation. This system could even to enable the simulation of neurogenesis.

[1]  Wolfgang Maass,et al.  Networks of Spiking Neurons: The Third Generation of Neural Network Models , 1996, Electron. Colloquium Comput. Complex..

[2]  Karlheinz Meier,et al.  A mixed-signal universal neuromorphic computing system , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

[3]  Enrico Macii,et al.  Top-Down Profiling of Application Specific Many-core Neuromorphic Platforms , 2015, 2015 IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip.

[4]  Jim D. Garside,et al.  Overview of the SpiNNaker System Architecture , 2013, IEEE Transactions on Computers.

[5]  Wofgang Maas,et al.  Networks of spiking neurons: the third generation of neural network models , 1997 .

[6]  Johannes Schemmel,et al.  A location-independent direct link neuromorphic interface , 2013, The 2013 International Joint Conference on Neural Networks (IJCNN).

[7]  Patrick Camilleri,et al.  Network traffic exploration on a many-core computing platform: SpiNNaker real-time traffic visualiser , 2015, 2015 11th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME).

[8]  Jim D. Garside,et al.  SpiNNaker—Programming Model , 2015, IEEE Transactions on Computers.

[9]  Tobias C. Potjans,et al.  The Cell-Type Specific Cortical Microcircuit: Relating Structure and Activity in a Full-Scale Spiking Network Model , 2012, Cerebral cortex.

[10]  Dharmendra S. Modha,et al.  A digital neurosynaptic core using embedded crossbar memory with 45pJ per spike in 45nm , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

[11]  Nikola Kasabov,et al.  Springer Handbook of Bio-/Neuro-Informatics , 2013 .

[12]  Cameron Patterson,et al.  Scalable event-driven native parallel processing: the SpiNNaker neuromimetic system , 2010, Conf. Computing Frontiers.

[13]  Steve B. Furber,et al.  An event-driven model for the SpiNNaker virtual synaptic channel , 2011, The 2011 International Joint Conference on Neural Networks.

[14]  Steve B. Furber,et al.  Modeling Spiking Neural Networks on SpiNNaker , 2010, Computing in Science & Engineering.

[15]  Pierre Yger,et al.  PyNN: A Common Interface for Neuronal Network Simulators , 2008, Front. Neuroinform..

[16]  Enrico Macii,et al.  Optimizing Network Traffic for Spiking Neural Network Simulations on Densely Interconnected Many-Core Neuromorphic Platforms , 2018, IEEE Transactions on Emerging Topics in Computing.