A 250 mV 8 kb 40 nm Ultra-Low Power 9T Supply Feedback SRAM (SF-SRAM)
暂无分享,去创建一个
Alexander Fish | Adam Teman | Omer Cohen | Lidor Pergament | A. Fish | A. Teman | L. Pergament | Omer Cohen
[1] Meng-Fan Chang,et al. A Differential Data-Aware Power-Supplied (D$^{2}$AP) 8T SRAM Cell With Expanded Write/Read Stabilities for Lower VDDmin Applications , 2009, IEEE Journal of Solid-State Circuits.
[2] A. Wang,et al. Modeling and sizing for minimum energy operation in subthreshold circuits , 2005, IEEE Journal of Solid-State Circuits.
[3] David Bol,et al. Impact of Technology Scaling on Digital Subthreshold Circuits , 2008, 2008 IEEE Computer Society Annual Symposium on VLSI.
[4] David Bol,et al. Robustness-aware sleep transistor engineering for power-gated nanometer subthreshold circuits , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.
[5] N. Vallepalli,et al. SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction , 2005, IEEE Journal of Solid-State Circuits.
[6] Jason Liu,et al. An 8T Subthreshold SRAM Cell Utilizing Reverse Short Channel Effect for Write Margin and Read Performance Improvement , 2007, 2007 IEEE Custom Integrated Circuits Conference.
[7] Anantha Chandrakasan,et al. Sub-threshold Design for Ultra Low-Power Systems , 2006, Series on Integrated Circuits and Systems.
[8] Kaushik Roy,et al. A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM , 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).
[9] R.W. Brodersen,et al. Methods for true energy-performance optimization , 2004, IEEE Journal of Solid-State Circuits.
[10] Kaushik Roy,et al. A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.
[11] Jan M. Rabaey,et al. SRAM leakage suppression by minimizing standby supply voltage , 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).
[12] S. Shimada,et al. Low-power embedded SRAM modules with expanded margins for writing , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..
[13] A.P. Chandrakasan,et al. A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy , 2008, IEEE Journal of Solid-State Circuits.
[14] A.P. Chandrakasan,et al. A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation , 2007, IEEE Journal of Solid-State Circuits.
[15] Kaushik Roy,et al. A feasibility study of subthreshold SRAM across technology generations , 2005, 2005 International Conference on Computer Design.
[16] Jan M. Rabaey,et al. Ultralow-Power Design in Near-Threshold Region , 2010, Proceedings of the IEEE.
[17] Jiajing Wang,et al. Analyzing static and dynamic write margin for nanometer SRAMs , 2008, Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08).
[18] Keshab K. Parhi,et al. Low power SRAM design using hierarchical divided bit-line approach , 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).
[19] Byung-Do Yang. A Low-Power SRAM Using Bit-Line Charge-Recycling for Read and Write Operations , 2010, IEEE Journal of Solid-State Circuits.
[20] Yu Cao,et al. Ultra-low-voltage robust design issues in deep-submicron CMOS , 2004, The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004..
[21] Jan M. Rabaey,et al. Digital Integrated Circuits: A Design Perspective , 1995 .
[22] Zheng Guo,et al. SRAM Read/Write Margin Enhancements Using FinFETs , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[23] A. Chandrakasan,et al. A 180-mV subthreshold FFT processor using a minimum energy design methodology , 2005, IEEE Journal of Solid-State Circuits.
[24] E. Vittoz,et al. An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications , 1995 .
[25] Kaushik Roy,et al. A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.
[26] Shunji Nakata,et al. Adiabatic SRAM with a large margin of VT variation by controlling the cell-power-line and word-line voltage , 2009, 2009 IEEE International Symposium on Circuits and Systems.
[27] Anantha P. Chandrakasan,et al. Subthreshold Circuit Techniques , 2004 .
[28] R.H. Dennard,et al. An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches , 2008, IEEE Journal of Solid-State Circuits.
[29] Eric A. Vittoz,et al. Weak inversion for ultra low-power and very low-voltage circuits , 2009, 2009 IEEE Asian Solid-State Circuits Conference.
[30] David Blaauw,et al. Energy-Efficient Subthreshold Processor Design , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[31] David Bol,et al. Interests and Limitations of Technology Scaling for Subthreshold Logic , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[32] A. Chandrakasan,et al. Analyzing static noise margin for sub-threshold SRAM in 65nm CMOS , 2005, Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005..
[33] A. Fish,et al. Digital subthreshold logic design - motivation and challenges , 2008, 2008 IEEE 25th Convention of Electrical and Electronics Engineers in Israel.
[34] Kaushik Roy,et al. A Low-Power SRAM Using Bit-Line Charge-Recycling , 2008, IEEE Journal of Solid-State Circuits.
[35] M. Sharifkhani,et al. SRAM Cell Stability: A Dynamic Perspective , 2009, IEEE Journal of Solid-State Circuits.
[36] C.H. Kim,et al. A Voltage Scalable 0.26 V, 64 kb 8T SRAM With V$_{\min}$ Lowering Techniques and Deep Sleep Mode , 2008, IEEE Journal of Solid-State Circuits.