Finite-Point Gate Model for Fast Timing and Power Analysis

This paper proposes a new finite-point based approach for efficient characterization of CMOS gate. The new method identifies several key points on the I-V and Q-V curves to define the behavior of the static CMOS gate. It targets performance metrics such as timing, short-circuit power and leakage in the presence of process variations. Experimental results validate the accuracy of the new approach and yields simulation speeds more than 15X faster than BSIM based library characterization.

[1]  Noel Menezes,et al.  A multi-port current source model for multiple-input switching effects in CMOS library cells , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[2]  Robert F. Pierret,et al.  Semiconductor device fundamentals , 1996 .

[3]  Yu Cao,et al.  Predictive Technology Model for Nano-CMOS Design Exploration , 2006, 2006 1st International Conference on Nano-Networks and Workshops.

[4]  Wei Chen,et al.  On Estimating Impact of Loading Effect on Leakage Current in Sub-65nm Scaled CMOS Circuits Based on Newton-Raphson Method , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[5]  Peng Li,et al.  A waveform independent gate model for accurate timing analysis , 2005, 2005 International Conference on Computer Design.

[6]  T. Serrano-Gotarredona,et al.  Systematic Width-and-Length Dependent CMOS Transistor Mismatch Characterization and Simulation , 1999 .

[7]  Martin D. F. Wong,et al.  Blade and razor: cell and interconnect delay analysis using current-based models , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[8]  Yu Cao,et al.  A robust finite-point based gate model considering process variations , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[9]  Ken Tseng,et al.  A robust cell-level crosstalk delay change analysis , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[10]  Lawrence T. Pileggi,et al.  A Gate-Delay Model for High-Speed CMOS Circuits , 1994, 31st Design Automation Conference.

[11]  Shahin Nazarian,et al.  A Current-based Method for Short Circuit Power Calculation under Noisy Input Waveforms , 2007, 2007 Asia and South Pacific Design Automation Conference.

[12]  Shahin Nazarian,et al.  Statistical logic cell delay analysis using a current-based model , 2006, 2006 43rd ACM/IEEE Design Automation Conference.