Design and implementation of Reconfigurable Stream Processor in multimedia applications

This paper proposed a Reconfigurable Stream Processor applied in multimedia applications. Based on the unique parallel stream processing framework and optimized algorithm mapping method, the reconfigurable processor exploits the parallelism of complex algorithms and provides a high flexibility during run-time to adapt to various applications. The architecture of processor is implemented and verified on the development board of ARM926EJS plus Xilinx Virtex-4XC4VLX80. A H.264 video codec is implemented to verify the reconfigurable architecture, achieving 58%~130% speed boost compared with traditional reconfigurable architectures such as MorphoSys and PACT.