A 25 Gb/s Hybrid-Integrated Silicon Photonic Source-Synchronous Receiver With Microring Wavelength Stabilization

Single-mode wavelength-division multiplexing (WDM) optical links are an attractive technology to meet the growing interconnect bandwidth demand in data center applications. This paper presents a multi-channel hybridintegrated photonic receiver based on microring drop filters and waveguide photodetectors implemented in a 130 nm SOI process and high-speed optical front-ends designed in 65 nm CMOS. The source-synchronous receiver utilizes an LC injection-locked oscillator (ILO) in the clock path for improved jitter filtering, while maintaining correlated jitter tracking with the data channels. Receiver sensitivity is improved with a large input-stage feedback resistor transimpedance amplifier (TIA) cascaded with an adaptively-tuned continuous-time linear equalizer (CTLE). In order to stabilize the microring drop filter resonance wavelength, a peak-detector-based thermal tuning loop is implemented with a 0.7 nm range at 43 μW/GHz efficiency. When tested with a waveguide photodetector with 0.45 A/W responsivity, the receiver achieves -8.0 dBm OMA sensitivity at a BER = 10-12 with a jitter tolerance corner frequency near 20 MHz and a per-channel power consumption of 17 mW including amortized clocking power.

[1]  Jochem Verbist,et al.  5 x 20 Gb/s heterogeneously integrated III-V on silicon electro-absorption modulator array with arrayed waveguide grating multiplexer. , 2015, Optics express.

[2]  Tim Moran,et al.  A quad 25Gb/s 270mW TIA in 0.13µm BiCMOS with <0.15dB crosstalk penalty , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[3]  David T. Neilson,et al.  Silicon photonic devices and integrated circuits , 2014 .

[4]  C L Schow,et al.  High-performance 850 nm VCSEL and photodetector arrays for 25 Gb/s parallel optical interconnects , 2010, 2010 Conference on Optical Fiber Communication (OFC/NFOEC), collocated National Fiber Optic Engineers Conference.

[5]  C. Patrick Yue,et al.  A 25Gbps, 2x-oversampling CDR using a zero-crossing linearizing phase detector , 2014, 2014 IEEE Radio Frequency Integrated Circuits Symposium.

[6]  Tanaka Shinsuke,et al.  A 25Gb/s Hybrid Integrated Silicon Photonic Transceiver in 28nm CMOS and SOI , 2015 .

[7]  James E. Jaussi,et al.  A Scalable 0.128–1 Tb/s, 0.8–2.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS , 2013, IEEE Journal of Solid-State Circuits.

[8]  Samuel Palermo,et al.  An 8–16 Gb/s, 0.65–1.05 pJ/b, Voltage-Mode Transmitter With Analog Impedance Modulation Equalization and Sub-3 ns Power-State Transitioning , 2014, IEEE Journal of Solid-State Circuits.

[9]  Dan Li,et al.  A Low-Noise Design Technique for High-Speed CMOS Optical Receivers , 2014, IEEE Journal of Solid-State Circuits.

[10]  Daniel Mahgerefteh,et al.  Techno-economic comparison of Silicon Photonics and multimode VCSELs , 2016, 2015 Optical Fiber Communications Conference and Exhibition (OFC).

[11]  Chen Sun,et al.  Addressing link-level design tradeoffs for integrated photonic interconnects , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

[12]  Ashok V. Krishnamoorthy,et al.  10-Gbps, 5.3-mW Optical Transmitter and Receiver Circuits in 40-nm CMOS , 2012, IEEE Journal of Solid-State Circuits.

[13]  Venkatesh Akella,et al.  Addressing system-level trimming issues in on-chip nanophotonic networks , 2011, 2011 IEEE 17th International Symposium on High Performance Computer Architecture.

[14]  Cheng Li,et al.  22.4 A 24Gb/s 0.71pJ/b Si-photonic source-synchronous receiver with adaptive equalization and microring wavelength stabilization , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[15]  Cheng Li,et al.  25Gb/s hybrid-integrated silicon photonic receiver with microring wavelength stabilization , 2015, 2015 Optical Fiber Communications Conference and Exhibition (OFC).

[16]  Binhao Wang,et al.  Silicon Photonic Transceiver Circuits With Microring Resonator Bias-Based Wavelength Stabilization in 65 nm CMOS , 2014, IEEE Journal of Solid-State Circuits.

[17]  R. G. Beausoleil,et al.  Large-scale integrated photonics for high-performance interconnects , 2011, IEEE Photonic Society 24th Annual Meeting.

[18]  Sanjeev K. Maheshwari,et al.  An 8.0-Gb/s HyperTransport Transceiver for 32-nm SOI-CMOS Server Processors , 2012, IEEE Journal of Solid-State Circuits.

[19]  Chen Sun,et al.  A Monolithically-Integrated Chip-to-Chip Optical Link in Bulk CMOS , 2015, IEEE J. Solid State Circuits.

[20]  A.C. Carusone,et al.  CMOS Oscillators for Clock Distribution and Injection-Locked Deskew , 2009, IEEE Journal of Solid-State Circuits.

[21]  Ashok V. Krishnamoorthy,et al.  A Monolithic 25-Gb/s Transceiver With Photonic Ring Modulators and Ge Detectors in a 130-nm CMOS SOI Process , 2012, IEEE Journal of Solid-State Circuits.

[22]  C. L. Schow,et al.  Ultra low power 10- to 25-Gb/s CMOS-driven VCSEL links , 2012, OFC/NFOEC.

[23]  Kunzhi Yu,et al.  DWDM silicon photonic transceivers for optical interconnect , 2015, 2015 IEEE Optical Interconnects Conference (OI).