Verifying a multiprocessor cache controller using random test generation
暂无分享,去创建一个
[1] Bell Cg,et al. Multis: a new class of multiprocessor computers. , 1985 .
[2] Randy H. Katz,et al. An in-cache address translation mechanism , 1986, ISCA '86.
[3] Alan Jay Smith,et al. Cache Memories , 1982, CSUR.
[4] David A. Patterson,et al. Reduced instruction set computers , 1985, CACM.
[5] Ieee Standards Board. IEEE standard for a simple 32-bit backplane bus : NuBus ; includes ANSI/IEEE Std 1101-1987, IEEE standard for mechanical core specifications for microcomputers , 1988 .
[6] James K. Archibald,et al. Cache coherence protocols: evaluation using a multiprocessor simulation model , 1986, TOCS.
[7] Jacob A. Abraham,et al. Test Generation for Microprocessors , 1980, IEEE Transactions on Computers.
[8] Frederic I. Parke,et al. N.mPc: A Retrospective , 1983, 20th Design Automation Conference Proceedings.
[9] Andrew R. Cherenson,et al. The Sprite network operating system , 1988, Computer.
[10] James R. Larus,et al. Design Decisions in SPUR , 1986, Computer.
[11] David A. Wood,et al. SPUR Memory System Architecture , 1988 .
[12] Randy H. Katz,et al. Implementing a cache consistency protocol , 1985, ISCA '85.
[13] Benjamin G. Zorn,et al. SPUR Lisp: Design and Implementation , 1987 .
[14] M.R. Mercer,et al. Algorithms for automatic test-pattern generation , 1988, IEEE Design & Test of Computers.
[15] P.M. Maurer. Design verification of the WE 32106 math accelerator unit , 1988, IEEE Design & Test of Computers.
[16] Richard J. Lipton,et al. Hints on Test Data Selection: Help for the Practicing Programmer , 1978, Computer.