An Ultra-Low-Power 16-Bit Second-Order Incremental ADC With SAR-Based Integrator for IoT Sensor Applications

This brief presents a 16-bit amplifier-free second-order incremental analog-to-digital converter (IADC2) for sensor applications. The proposed IADC2 employs a power efficient successive approximation register (SAR)-based integrator for the charge transfer operation, which consumes dynamic power only, instead of using power-consuming operational transconductance amplifiers that consume a high static current. The proposed amplifier thus achieves ultra-low-power consumption in low-frequency operation. In addition, the charge redistribution period of a capacitor digital-to-analog converter (CDAC) in the SAR-based integrator is split in a time-interleaving way, such that the CDAC can be shared by the first and second integrators. A test chip, including the proposed IADC2, was fabricated using 0.18-<inline-formula> <tex-math notation="LaTeX">${\mu }\text{m}$ </tex-math></inline-formula> standard CMOS process technology. The measurement results show that the proposed IADC2 achieves a differential nonlinearity of −0.51/+0.74 LSB and an integral nonlinearity of −3.12/+0.24$ LSB. In addition, the measured maximum signal-to-noise ratio, and an effective number of bits are 93.4 dB and 15.22-bit for the dc signal, respectively. The measured power consumption is 0.24 <inline-formula> <tex-math notation="LaTeX">${\mu }\text{W}$ </tex-math></inline-formula> at a sampling frequency of 10 kHz. Therefore, the proposed IADC2 is suitable for various sensor applications requiring ultra-low-power consumption.