Ram Allocation Algorithm for Video Processing Applications on FPGA

This paper presents an algorithm for the allocation of on-chip FPGA Block RAMs for the implementation of Real-Time Video Processing Systems. The effectiveness of the algorithm is shown through the ...

[1]  W.F.J. Verhaegh,et al.  Allocation of multiport memories for hierarchical data streams , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[2]  L. De Marchi,et al.  Comparison of a programmable DSP and FPGA implementation for a wavelet-based denoising algorithm , 2003, 2003 46th Midwest Symposium on Circuits and Systems.

[3]  Fan Yang,et al.  Implementation of an RBF neural network on embedded systems: real-time face tracking and identity verification , 2003, IEEE Trans. Neural Networks.

[4]  H. De Man,et al.  Optimization of memory organization and hierarchy for decreased size and power in video and image processing systems , 1995, Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing.

[5]  Maya Gokhale,et al.  Automatic allocation of arrays to memories in FPGA processors with multiple memory banks , 1999, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375).

[6]  Wayne Luk,et al.  Memory access optimisation for reconfigurable systems , 2001 .

[7]  Nikil D. Dutt,et al.  High-level library mapping for memories , 2000, TODE.

[8]  Bruce A. Draper,et al.  Accelerated image processing on FPGAs , 2003, IEEE Trans. Image Process..

[9]  Benny Thörnberg,et al.  A comparison between local and global memory allocation for FPGA implementation of real-time video processing systems , 2004 .

[10]  Francky Catthoor,et al.  Custom Memory Management Methodology , 1998, Springer US.

[11]  Benny Thörnberg,et al.  Automatic Hardware Synthesis of Spatial Memory Models for Real-Time Image Processing Systems , 2003 .

[12]  Hugo De Man,et al.  Background memory area estimation for multidimensional signal processing systems , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[13]  Francky Catthoor,et al.  Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design , 1998 .

[14]  Catherine H. Gebotys Low energy memory and register allocation using network flow , 1997, DAC.

[15]  Taewhan Kim,et al.  Memory allocation and mapping in high-level synthesis - an integrated approach , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[16]  Viraphol Chaiyakul,et al.  An algorithm for array variable clustering , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[17]  Herman Schmit,et al.  Synthesis of application-specific memory designs , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[18]  Pedro C. Diniz,et al.  Compiler reuse analysis for the mapping of data in FPGAs with RAM blocks , 2004, Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921).

[19]  Pedro C. Diniz,et al.  Automatic synthesis of data storage and control structures for FPGA-based computing engines , 2000, Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871).