Selective etching of HfN gate electrode for HfN/HfSiON gate stack in-situ formations

In order to fabricate metal gate/high-k gate stacks utilizing ECR sputtering, selective etching of HfN gate electrodes was investigated. It was found that etching rates of HfN gate electrodes at room temperature were 2.9 and 0.23nm/s for DHF (1%) and the mixed solution of HF:H2O2:H2O = 1:2:40, respectively. In addition, the etching selectivity for HfN/HfSiON was relatively high, such as the ratio of 65 which was 3 times higher than that of DHF (1%) by the mixed solution. After the in-situ formation of HfN/HfSiON layers on p-Si(100) and post deposition annealing (PDA), pattering of HfN was carried out utilizing the selective etching process. In case the PDA of 800°C/15s, the MOS diodes were found to be successfully fabricated, and the equivalent oxide thickness (EOT) of 0.56nm, and the leakage current at VFB-1 V of 1.3A/cm2 were obtained.

[1]  J. Autran,et al.  Properties of amorphous and crystalline Ta2O5 thin films deposited on Si from a Ta(OC2H5)5 precursor , 1998 .

[2]  Doo Young Yang,et al.  Interfacial reaction between chemically vapor-deposited HfO2 thin films and a HF-cleaned Si substrate during film growth and postannealing , 2002 .

[3]  R. Chau,et al.  A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging , 2007, 2007 IEEE International Electron Devices Meeting.

[4]  Takahiro Sano,et al.  HfOxNy Thin-Film Formation on Three-Dimensional Si Structure Utilizing Electron Cyclotron Resonance Sputtering , 2009 .

[5]  S.-J. Choi,et al.  A 32nm SoC platform technology with 2nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[6]  J. Bonnouvrier,et al.  Competitive and cost effective high-k based 28nm CMOS technology for low power applications , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[7]  X. Chen,et al.  A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process , 2008, 2008 Symposium on VLSI Technology.

[8]  T. Pan,et al.  Work Function Adjustment by Nitrogen Incorporation in HfN x Gate Electrode with Post Metal Annealing , 2006 .

[9]  M. Yamaguchi,et al.  Formation of HfSiON/SiO/sub 2//Si-substrate gate stack with low leakage current for high-performance high-/spl kappa/ MISFETs , 2006, IEEE Transactions on Electron Devices.

[10]  S. Saito,et al.  Analytical quantum mechanical model for accumulation capacitance of MOS structures , 2002, IEEE Electron Device Letters.

[11]  Takahiro Sano,et al.  In situ Formation of HfN/HfSiON Gate Stacks with 0.5 nm Equivalent Oxide Thickness Utilizing Electron Cyclotron Resonance Plasma Sputtering on Three-Dimensional Si Structures , 2011 .

[12]  Wen-Jie Qi,et al.  Characteristics of TaN gate MOSFET with ultrathin hafnium oxide (8 /spl Aring/-12 /spl Aring/) , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).