Interconnect Synthesis for Lithography and Manufacturability in Deep Submicron Design

Effective design for large VLSI systems requires abstraction; problems are simply too complex to be addressed directly. To obtain good results, it is necessary that the abstractions still capture the basic nature of the problem. Deep submicron lithography has placed new constraints on circuit layout; these constraints are frequently counterintuitive, and are hard to model with current design rules. When design tools ignore the constraints, there is a need for a great deal of “back end” work to fix violations–the difficulty of these fixes has resulted in a push towards very restrictive design rules. To enable aggressive design without major violations, better abstractions are needed. In this paper, we focus on circuit interconnect, and develop a “straw man” approach to considering the lithography and manufacturability challenges of deep submicron design. We propose Mead-and-Conway style rules, and the concept of a “virtual layer” to separate mask-based constraints from silicon-based constraints. We also discuss a prototype routing tool that uses the virtual layer approach.