Fast convergence stochastic LDPC decoder based on edge memory structure

In recent years, the LDPC decoder based on stochastic calculation has been becoming a hot topic, and the re-randomization structure based on edge memory for the stochastic LDPC decoder shows great advantages over performance and complexity compared with the traditional decoders. However, latching issue is also the main challenge for the stochastic LDPC decoders with edge memory structure, similar to stochastic LDPC decoders with other structures. Frequent latching state results in a low information updating efficiency, which reduces decoding performance and convergence speed. In order to speed up the information updating efficiency of the stochastic decoder, in this paper, we propose a dual memory parallel update structure for edge memory. Based on the proposed structure, the efficiency of information convergence is greatly accelerated with acceptable hardware cost. And the decoding performance and latency are also improved.