Low-power single-bit full adder cells

The single-bit full adder is one of the main components in almost all logic structures. The performance of logic structures is highly dependent on the adder cells. This paper discusses the performance of single-bit full adders and presents a performance analysis for those cells in CMOS technology. Fourteen single-bit full adders and three new adders, a total of different adder cells, are analyzed in terms of power and delay using 0.35, 0.25 and 0.18 µm TSMC CMOS technology. In addition, this paper discusses the charging-capability parameter of the adder cells, which represents the fan-out of each cell. The charging-capability parameter is capable of describing the performance of the adder cell in a large, as yet unbuilt structure. Hence, the performance analysis of the single-bit full adder relates the design to power, delay, and charging capability of the logic components.

[1]  Magdy A. Bayoumi,et al.  A 10-transistor low-power high-speed full adder cell , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[2]  Mohamed I. Elmasry,et al.  Circuit techniques for CMOS low-power high-performance multipliers , 1996 .

[3]  Makoto Suzuki,et al.  A 1.5-ns 32-b CMOS ALU in double pass-transistor logic , 1993 .

[4]  E. Abu-Shama,et al.  A new cell for low power adders , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[5]  Magdy A. Bayoumi,et al.  Performance evaluation of 1-bit CMOS adder cells , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[6]  Tormod Njdstad.  POWER CONSUMPTION AND PERFORMANCE OF LOW-VOLTAGE BIT-SERIAL ADDERS , 1996 .

[7]  Uming Ko,et al.  Low-power design techniques for high-performance CMOS adders , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[8]  Anantha P. Chandrakasan,et al.  Low-power CMOS digital design , 1992 .

[9]  Earl E. Swartzlander,et al.  Estimating the power consumption of CMOS adders , 1993, Proceedings of IEEE 11th Symposium on Computer Arithmetic.

[10]  A. Wu.  High performance adder cell for low power pipelined multiplier , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[11]  Haomin Wu,et al.  A new design of the CMOS full adder , 1992 .

[12]  Tat Chee Ave.  HIGH PERFORMANCE ADDER CELL FOR LOW POWER PIPELINED MULTIPLIER , 1996 .

[13]  Kazuo Yano,et al.  A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logic , 1990 .

[14]  D. Radhakrishnan,et al.  Low-voltage low-power CMOS full adder , 2001 .

[15]  Mary Jane Irwin,et al.  Power-delay characteristics of CMOS adders , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[16]  Magdy Bayoumi,et al.  A novel high-performance CMOS 1-bit full-adder cell , 2000 .

[17]  E.J. Aas,et al.  Power consumption and performance of low-voltage bit-serial adders , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[18]  Wu-Shiung Feng,et al.  New efficient designs for XOR and XNOR functions on the transistor level , 1994, IEEE J. Solid State Circuits.

[19]  Takayasu Sakurai,et al.  A high speed, low power, swing restored pass-transistor logic based multiply and accumulate circuit for multimedia applications , 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.