Integrated Frequency Synthesizers for Wireless Systems

The increasingly demanding performance requirements of communications systems, as well as problems posed by the continued scaling of silicon technology, present numerous challenges for the design of frequency synthesizers in modern transceivers. This book contains everything you need to know for the efficient design of frequency synthesizers for today's communications applications. If you need to optimize performance and minimize design time, you will find this book invaluable. Using an intuitive yet rigorous approach, the authors describe simple analytical methods for the design of phase locked loop (PLL) frequency synthesizers using scaled silicon CMOS and bipolar technologies. The entire design process, from system-level specification to layout, is covered comprehensively. Practical design examples are included, and implementation issues are addressed. A key problem-solving resource for practitioners in IC design, the book will also be of interest to researchers and graduate students in electrical engineering.

[1]  Chen-Yi Lee,et al.  Design of a wide-band frequency synthesizer based on TDC and DVC techniques , 2002, IEEE J. Solid State Circuits.

[2]  J. Long,et al.  The modeling, characterization, and design of monolithic inductors for silicon RF IC's , 1997, IEEE J. Solid State Circuits.

[3]  Christer Svensson,et al.  High-speed CMOS circuit technique , 1989 .

[4]  Roland E. Best.  Phase-Locked Loops , 1984 .

[5]  Lawrence E. Larson,et al.  Cdma Mobile Radio Design , 2000 .

[6]  Jerry Lin,et al.  A low-phase-noise 0.004-ppm/step DCXO with guaranteed monotonicity in the 90-nm CMOS process , 2005, IEEE Journal of Solid-State Circuits.

[7]  R. Castello,et al.  A metal-oxide-semiconductor varactor , 1999, IEEE Electron Device Letters.

[8]  Qiuting Huang,et al.  Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks , 1996 .

[9]  A. Lacaita,et al.  A dual-band frequency synthesizer for 802.11a/b/g with fractional-spur averaging technique , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[10]  Carlo Samori,et al.  Spectrum folding and phase noise in LC tuned oscillators , 1998 .

[11]  T. Riley,et al.  Delta-sigma modulation in fractional-N frequency synthesis , 1993 .

[12]  F. Gardner,et al.  Charge-Pump Phase-Lock Loops , 1980, IEEE Trans. Commun..

[13]  J. W. Scott,et al.  z-domain model for discrete-time PLL's , 1988 .

[14]  M. Lax.  Classical Noise. V. Noise in Self-Sustained Oscillators , 1967 .

[15]  Gabor C. Temes,et al.  Oversampling delta-sigma data converters : theory, design, and simulation , 1992 .

[16]  Wonchan Kim,et al.  Comparison frequency doubling and charge pump matching techniques for dual-band ΔΣ fractional-N frequency synthesizer , 2005 .

[17]  Behzad Razavi,et al.  A single-chip dual-band direct-conversion IEEE 802.11a/b/g WLAN transceiver in 0.18-μm CMOS , 2005 .

[18]  M. Zargari,et al.  A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11a/b/g wireless LAN , 2004, IEEE Journal of Solid-State Circuits.

[19]  P. Schvan,et al.  A balanced 1.5 GHz voltage controlled oscillator with an integrated LC resonator , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[20]  R. Castello,et al.  A 700-kHz bandwidth /spl Sigma//spl Delta/ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications , 2004, IEEE Journal of Solid-State Circuits.

[21]  Sebastian Magierowski,et al.  CMOS LC-oscillator phase-noise analysis using nonlinear models , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[22]  Robert G. Meyer,et al.  Relationship between frequency response and settling time of operational amplifiers , 1974 .

[23]  Jan Craninckx,et al.  A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-/spl mu/m CMOS , 1996 .

[24]  Nikolaus Klemmer,et al.  Enhanced phase noise modeling of fractional-N frequency synthesizers , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[25]  A. Demir,et al.  Phase noise in oscillators: a unifying theory and numerical methods for characterization , 2000 .

[26]  Dan H. Wolaver,et al.  Phase-Locked Loop Circuit Design , 1991 .

[27]  Floyd M. Gardner,et al.  Phaselock techniques , 1984, IEEE Transactions on Systems, Man, and Cybernetics.

[28]  W.F. Egan,et al.  Modeling phase noise in frequency dividers , 1990, IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control.

[29]  K. Soumyanath,et al.  10 GHz, 20 mW, fast locking, adaptive gain PLLs with on-chip frequency calibration for agile frequency synthesis in a 0.18 /spl mu/m digital CMOS process , 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).

[30]  T. Nakagawa,et al.  A phase noise reduction technique for MMIC frequency synthesizers that uses a new pulse generator LSI , 1994 .

[31]  O.H. Murphy,et al.  Design of multiple-metal stacked inductors incorporating an extended physical model , 2005, IEEE Transactions on Microwave Theory and Techniques.

[32]  C. Tsui,et al.  A physical analytical model of multilayer on-chip inductors , 2005, IEEE Transactions on Microwave Theory and Techniques.

[33]  A. Abidi,et al.  Physical processes of phase noise in differential LC oscillators , 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

[34]  W. R. Eisenstadt,et al.  S-parameter-based IC interconnect transmission line characterization , 1992 .

[35]  K. Kurokawa,et al.  Noise in Synchronized Oscillators , 1968 .

[36]  Robert G. Meyer,et al.  A low-noise, low-power VCO with automatic amplitude control for wireless applications , 1999, IEEE J. Solid State Circuits.

[37]  Jaijeet Roychowdhury,et al.  Cyclostationary noise analysis of large RF circuits with multitone excitations , 1998 .

[38]  P. A. H. Hart.  Bipolar and bipolar-MOS integration , 1994 .

[39]  A. Hajimiri,et al.  Jitter and phase noise in ring oscillators , 1999, IEEE J. Solid State Circuits.

[40]  Thomas H. Lee,et al.  The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES , 2003 .

[41]  Ana García Armada,et al.  Understanding the effects of phase noise in orthogonal frequency division multiplexing (OFDM) , 2001, IEEE Trans. Broadcast..

[42]  R.W. Brodersen,et al.  Millimeter-wave CMOS design , 2005, IEEE Journal of Solid-State Circuits.

[43]  S. Pellerano,et al.  Phase noise in digital frequency dividers , 2004, IEEE Journal of Solid-State Circuits.

[44]  C.S. Vaucher,et al.  A family of low-power truly modular programmable dividers in standard 0.35-/spl mu/m CMOS technology , 2000, IEEE Journal of Solid-State Circuits.

[45]  Vadim Manassewitsch,et al.  Frequency Synthesizers: Theory and Design , 1976 .

[46]  B. Razavi,et al.  A stabilization technique for phase-locked frequency synthesizers , 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).

[47]  B. Razavi.  Monolithic phase-locked loops and clock recovery circuits : theory and design , 1996 .

[48]  William C. Lindsey,et al.  SYNCHRONIZATION SYSTEMS in Communication and Control , 1972 .

[49]  P. Andreani,et al.  On the use of MOS varactors in RF VCOs , 2000, IEEE Journal of Solid-State Circuits.

[50]  K. K. Clarke,et al.  Communication Circuits: Analysis and Design , 1971 .

[51]  Michiel Steyaert,et al.  A 1.8-GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors , 1997, IEEE J. Solid State Circuits.

[52]  Venceslav F. Kroupa,et al.  Phase Lock Loops and Frequency Synthesis , 2003 .

[53]  Behzad Razavi,et al.  Design of Analog CMOS Integrated Circuits , 1999 .

[54]  I. Vassiliou,et al.  A single-chip digitally calibrated 5.15-5.825-GHz 0.18-μm CMOS transceiver for 802.11a wireless LAN , 2003, IEEE J. Solid State Circuits.

[55]  M. Steyaert,et al.  A CMOS monolithic ΔΣ-controlled fractional-N frequency synthesizer for DCS-1800 , 2002, IEEE J. Solid State Circuits.

[56]  M. Keaveney,et al.  A 10/spl mu/s fast switching PLL synthesizer for a GSM/EDGE base-station , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[57]  F. Kaertner.  Determination of the correlation spectrum of oscillators with low noise , 1989 .

[58]  F. Svelto,et al.  A fully integrated 0.18-/spl mu/m CMOS direct conversion receiver front-end with on-chip LO for UMTS , 2004, IEEE Journal of Solid-State Circuits.

[59]  Michael H. Perrott,et al.  A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation , 1997, IEEE J. Solid State Circuits.

[60]  K. S. Kundert.  Introduction to RF simulation and its application , 1999 .

[61]  M. Zuta.  A NEW PLL WITH FAST SETTLING TIME AND LOW PHASE NOISE , 1998 .

[62]  Juha Kostamovaara,et al.  Techniques for in-band phase noise reduction in /spl Delta//spl Sigma/ synthesizers , 2003 .

[63]  Ali Hajimiri,et al.  A general theory of phase noise in electrical oscillators , 1998 .

[64]  D. Leeson.  A simple model of feedback oscillator noise spectrum , 1966 .

[65]  S.S. Wong,et al.  Analysis and synthesis of on-chip spiral inductors , 2005, IEEE Transactions on Electron Devices.

[66]  R. Weigel,et al.  A fully integrated VCO at 2 GHz , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[67]  A. Fard,et al.  A study of phase noise in colpitts and LC-tank CMOS oscillators , 2005, IEEE Journal of Solid-State Circuits.

[68]  F. L. Walls,et al.  Characterization of frequency stability in precision frequency sources , 1991, Proc. IEEE.

[69]  Robert G. Meyer,et al.  High-frequency phase-locked loops in monolithic bipolar technology , 1989 .

[70]  E. Klumperink,et al.  Reducing MOSFET 1/f noise and power consumption by switched biasing , 1999, IEEE Journal of Solid-State Circuits.

[71]  T. Melly,et al.  Design of high-Q varactors for low-power wireless applications using a standard CMOS process , 2000, IEEE Journal of Solid-State Circuits.

[72]  Lars C. Jansson,et al.  A wideband 2.4-GHz delta-sigma fractional-NPLL with 1-Mb/s in-loop modulation , 2004, IEEE Journal of Solid-State Circuits.

[73]  M.H. Perrott,et al.  A 1-MHZ bandwidth 3.6-GHz 0.18-/spl mu/m CMOS fractional-N synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noise , 2006, IEEE Journal of Solid-State Circuits.

[74]  D. Butterfield,et al.  Prediction of fractional-N spurs for UHF PLL frequency synthesizers , 1999, 1999 IEEE MTT-S International Topical Symposium on Technologies for Wireless Applications (Cat. No. 99TH8390).

[75]  Salvatore Levantino,et al.  A 2-V 2.5-GHz-104-dBc/Hz at 100 kHz fully integrated VCO with wide-band low-noise automatic amplitude control loop , 2001, IEEE J. Solid State Circuits.

[76]  C. Sodini,et al.  The impact of device type and sizing on phase noise mechanisms , 2005, IEEE J. Solid State Circuits.

[77]  Venceslav F. Kroupa,et al.  Jitter and phase noise in frequency dividers , 2001, IEEE Trans. Instrum. Meas..

[78]  Ulrich L. Rohde,et al.  Microwave and wireless synthesizers: theory and design , 1997 .

[79]  J. Stensby,et al.  Phase-Locked Loops: Theory and Applications , 1997 .

[80]  Behzad Razavi,et al.  A study of phase noise in CMOS oscillators , 1996, IEEE J. Solid State Circuits.

[81]  Alain Blanchard,et al.  Phase-Locked Loops: Application to Coherent Receiver Design , 1976, IEEE Transactions on Systems, Man, and Cybernetics.

[82]  H. Greenhouse,et al.  Design of Planar Rectangular Microelectronic Inductors , 1974 .

[83]  Ali M. Niknejad,et al.  Analysis, design, and optimization of spiral inductors and transformers for Si RF ICs , 1998, IEEE J. Solid State Circuits.

[84]  R. B. Nubling,et al.  A high-speed multimodulus HBT prescaler for frequency synthesizer applications , 1991 .

[85]  Bram De Muer,et al.  On the analysis of ΔΣ fractional-N frequency synthesizers for high-spectral purity , 2003, IEEE Trans. Circuits Syst. II Express Briefs.

[86]  P. Larsson.  High-speed architecture for a programmable frequency divider and a dual-modulus prescaler , 1996 .

[87]  Giuseppe Palmisano,et al.  An integrated RF transceiver for DECT application , 2001 .

[88]  B.-S. Song,et al.  A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order /spl Delta//spl Sigma/ modulator , 2000, IEEE Journal of Solid-State Circuits.

[89]  C. Samori,et al.  Phase noise degradation at high oscillation amplitudes in LC-tuned VCO's , 2000, IEEE Journal of Solid-State Circuits.

[90]  G. C. Gillette,et al.  Digiphase Synthesizer , 1969 .

[91]  Theodore I. Kamins,et al.  Device Electronics for Integrated Circuits , 1977 .

[92]  H.C. Luong,et al.  A 1-V 5.2-GHz CMOS synthesizer for WLAN applications , 2004, IEEE Journal of Solid-State Circuits.

[93]  Behzad Razavi.  Phase-Locking In High-Performance Systems , 2003 .

[94]  B. Bisanti,et al.  An 18-mW 2.5-GHz/900-MHz BiCMOS dual frequency synthesizer with < 10-Hz RF carrier resolution , 2000, Proceedings of the 26th European Solid-State Circuits Conference.

[95]  O. Moreira-Tamayo,et al.  All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS , 2004, IEEE Journal of Solid-State Circuits.

[96]  Yu Cao,et al.  Frequency-independent equivalent-circuit model for on-chip spiral inductors , 2003 .

[97]  Salvatore Levantino,et al.  A varactor configuration minimizing the amplitude-to-phase noise conversion in VCOs , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[98]  K. O. Kenneth,et al.  A low-phase-noise and low-power multiband CMOS voltage-controlled oscillator , 2005 .

[99]  M. Biyani,et al.  A high-speed CMOS dual-phase dynamic-pseudo NMOS ((DP)/sup 2/) latch and its application in a dual-modulus prescaler , 1999 .

[100]  M. Tiebout,et al.  Low-power low-phase-noise differentially tuned quadrature VCO design in standard CMOS , 2001, IEEE J. Solid State Circuits.

[101]  R. Adler,et al.  A Study of Locking Phenomena in Oscillators , 1946, Proceedings of the IRE.

[102]  E. Hegazi,et al.  A 17 mW transmitter and frequency synthesizer for 900 MHz GSM fully integrated in 0.35-/spl mu/m CMOS , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

[103]  M. Tiebout,et al.  MOS varactors with n- and p-type gates and their influence on an LC-VCO in digital CMOS , 2003, IEEE J. Solid State Circuits.

[104]  Salvatore Levantino,et al.  AM-to-PM conversion in varactor-tuned oscillators , 2002 .

[105]  Mitchell D. Trott,et al.  A Modeling Approach for – Fractional- N Frequency Synthesizers Allowing Straightforward Noise Analysis , 2001 .

[106]  Chun-Huat Heng,et al.  A 1.8-GHz CMOS fractional-N frequency synthesizer with randomized multiphase VCO , 2003 .

[107]  V. Boccuzzi,et al.  A 3.5-GHz PLL for fast low-IF/zero-IF LO switching in an 802.11 transceiver , 2005, IEEE Journal of Solid-State Circuits.

[108]  Milton Abramowitz,et al.  Handbook of Mathematical Functions with Formulas, Graphs, and Mathematical Tables , 1964 .

[109]  O. Kenneth,et al.  Estimation methods for quality factors of inductors fabricated in silicon integrated circuit process technologies , 1998, IEEE J. Solid State Circuits.

[110]  H.R. Rategh,et al.  A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver , 2000, IEEE Journal of Solid-State Circuits.

[111]  C. Muschallik.  Influence of RF oscillators on an OFDM signal , 1995 .

[112]  William F. Egan,et al.  Frequency synthesis by phase lock , 1981 .

[113]  T. Kwasniewski,et al.  CMOS high-speed dual-modulus frequency divider for RF frequency synthesis , 1995 .

[114]  G. Li Puma,et al.  A 2-GHz low-phase-noise integrated LC-VCO set with flicker-noise upconversion minimization , 2000, IEEE Journal of Solid-State Circuits.

[115]  Byeong-Ha Park,et al.  A /spl Sigma/-/spl Delta/ fractional-N frequency synthesizer using a wide-band integrated VCO and a fast AFC technique for GSM/GPRS/WCDMA applications , 2004 .

[116]  Salvatore Levantino,et al.  Fast-switching analog PLL with finite-impulse response , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[117]  Zhiping Yu,et al.  Scalable compact circuit model and synthesis for RF CMOS spiral inductors , 2006 .

[118]  Marvin K. Simon,et al.  Phase-locked loops and their application , 1978 .

[119]  A. Abidi,et al.  Large suspended inductors on silicon and their use in a 2- mu m CMOS RF amplifier , 1993, IEEE Electron Device Letters.

[120]  Edgar Sanchez-Sinencio,et al.  A 2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier , 2003, IEEE J. Solid State Circuits.

[121]  J.C. Guo,et al.  A broadband and scalable model for on-chip inductors incorporating substrate and conductor loss effects , 2005, 2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium - Digest of Papers.

[122]  W. A. Edson.  Noise in Oscillators , 1960, Proceedings of the IRE.

[123]  Salvatore Levantino,et al.  Frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion , 2002, IEEE J. Solid State Circuits.

[124]  Bram Nauta,et al.  Architectures for RF Frequency Synthesizers , 2002 .

[125]  E. Hegazi,et al.  23.4 A Filtering Technique to Lower Oscillator Phase Noise , 2008 .

[126]  W.A.M. Van Noije,et al.  A 1.6-GHz dual modulus prescaler using the extended true-single-phase-clock CMOS circuit technique (E-TSPC) , 1999, IEEE J. Solid State Circuits.

[127]  Behzad Razavi,et al.  Stacked inductors and transformers in CMOS technology , 2001 .

[128]  Howard C. Luong,et al.  A 2-V 900-MHz monolithic CMOS dual-loop frequency synthesizer for GSM receivers , 2001 .

[129]  Lorenzo Piazzo,et al.  Analysis of phase noise effects in OFDM modems , 2002, IEEE Trans. Commun..

[130]  Chris J. M. Verhoeven,et al.  A new low-noise 100-MHz balanced relaxation oscillator , 1990 .

[131]  M. A. Copeland,et al.  Design and realization of a digital /spl Delta//spl Sigma/ modulator for fractional-n frequency synthesis , 1999 .

[132]  Behzad Razavi,et al.  RF Microelectronics , 1997 .

[133]  W. Rhee,et al.  Design of high-performance CMOS charge pumps in phase-locked loops , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[134]  A. Abidi,et al.  Varactor characteristics, oscillator tuning curves, and AM-FM conversion , 2003, IEEE J. Solid State Circuits.

[135]  A. Hajimiri,et al.  Design issues in CMOS differential LC oscillators , 1999, IEEE J. Solid State Circuits.

[136]  Roland E. Best.  Phase-locked loops : design, simulation, and applications , 2003 .

[137]  B. Miller,et al.  A multiple modulator fractional divider , 1991 .

[138]  James A. Crawford.  Frequency Synthesizer Design Handbook , 1994 .

[139]  Asad A. Abidi,et al.  RF-CMOS oscillators with switched tuning , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

[140]  N. Krishnapura,et al.  A 5.3-GHz programmable divider for HiPerLAN in 0.25-/spl mu/m CMOS , 2000, IEEE Journal of Solid-State Circuits.

[141]  Franz X. Kärtner,et al.  Analysis of white and f-α noise in oscillators , 1990, Int. J. Circuit Theory Appl..

[142]  Baohong Cheng,et al.  A single-chip dual-band direct-conversion IEEE 802.11a/b/g WLAN transceiver in 0.18-/spl mu/m CMOS , 2005, IEEE Journal of Solid-State Circuits.

[143]  Ian Galton,et al.  Delta-sigma data conversion in wireless transceivers , 2002 .

[144]  Ook Kim,et al.  A 1.8-GHz self-calibrated phase-locked loop with precise I/Q matching , 2001, IEEE J. Solid State Circuits.

[145]  A. Hajimiri,et al.  A fully integrated 24-GHz phased-array transmitter in CMOS , 2005, IEEE Journal of Solid-State Circuits.

[146]  Peter R. Kinget,et al.  A 5.3GHz programmable divider for HiPerLAN in 0.25µm CMOS , 1999 .

[147]  M. Shoji.  FFT scaling in Domino CMOS gates , 1985 .

[148]  D. Pozar.  Microwave Engineering , 1990 .