On the CSC property of signal transition graph specifications for asynchronous circuit design

This paper proposes a new approach for asynchronous logic synthesis from Signal Transition Graph (STG) specifications. The Complete State Coding (CSC) property of STGs is a necessary condition to get a circuit implementation from an STG. We present a novel method to check the CSC property of STGs. We also discuss some heuristics which automatically modify the STG so that the CSC property is satisfied. Our approach gives the designer some freedom to specify in what way a given STG is modified. Experimental results on a large set of benchmarks indicate a clear improvement over previous methods both in terms of time taken and in the reduction of the two level area literals.

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