Test and repair of large embedded DRAMs. I
暂无分享,去创建一个
[1] Detlev Richter,et al. How we test Siemens Embedded DRAM Cores , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).
[2] G. M. Lattimore,et al. A 576 K 3.5-ns access BiCMOS ECL static RAM with array built-in self-test , 1992 .
[3] R. Kho,et al. An ASIC library granular DRAM macro with built-in self test , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).
[4] Robert C. Aitken. On-chip versus off-chip test: an artificial dichotomy , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).
[5] Howard Leo Kalter,et al. Processor-based built-in self-test for embedded DRAM , 1998, IEEE J. Solid State Circuits.
[6] Francky Catthoor,et al. Guest Editors' Intoduction: The New World of Large Embedded Memories , 2001, IEEE Des. Test Comput..
[7] Rochit Rajsuman. Design and Test of Large Embedded Memories: An Overview , 2001, IEEE Des. Test Comput..
[8] Rochit Rajsuman. System-On-A-Chip: Design and Test , 2000 .
[9] Hideto Hidaka,et al. A built-in self-repair analyzer (CRESTA) for embedded DRAMs , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).
[10] John E. Barth,et al. Embedded DRAM built in self test and methodology for test insertion , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).