Design of multi-core rasterizer for parallel processing

As resolution for displays is recently more and more increasing, the amount of data and calculation that graphic hardware needs to process are also increasing. Especially the amount of data processing by Rasterizer is rapidly increasing. This paper used an algorism using coordinates in center of gravity and area for triangle instead of using bilinear algorism [1] used by conventional interpolation, which is to make it easier for parallel processing by Rasterizer. This paper implemented designed Rasterizer under FPGA environment and compared it with conventional Rasterizer and verified it. This Rasterizer is proved to have approximately 50% higher performance compared to conventional one.

[1]  Hoi-Jun Yoo,et al.  Mobile 3D Graphics SoC: From Algorithm to Chip , 2010 .

[2]  Seongmo Park,et al.  Implementation of 3D graphics accelerator using full pipeline scheme on FPGA , 2008, 2008 International SoC Design Conference.

[3]  Donald G. Bailey,et al.  A novel approach to real-time bilinear interpolation , 2004, Proceedings. DELTA 2004. Second IEEE International Workshop on Electronic Design, Test and Applications.

[4]  Jae-Chang Kwak,et al.  A design of a 3D graphics rasterizer with a culling and clipping , 2007, TENCON 2007 - 2007 IEEE Region 10 Conference.

[5]  Taeyoung Lee,et al.  An efficient JPEG decoding and scaling method for digital TV platforms , 2012, 2012 International SoC Design Conference (ISOCC).