Digital subthreshold logic design - motivation and challenges
暂无分享,去创建一个
A. Fish | O. Yadid-Pecht | A. Teman | S. Fisher | D. Vaysman | A. Gertsman
[1] Saibal Mukhopadhyay,et al. Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits , 2003, Proc. IEEE.
[2] Benton H. Calhoun. Low energy digital circuit design using sub-threshold operation , 2005 .
[3] Anantha Chandrakasan,et al. Sub-threshold Design for Ultra Low-Power Systems , 2006, Series on Integrated Circuits and Systems.
[4] Siegfried Selberherr,et al. Ultra-low-power CMOS technologies , 1996, 1996 International Semiconductor Conference. 19th Edition. CAS'96 Proceedings.
[5] Anantha P. Chandrakasan,et al. Low-power CMOS digital design , 1992 .
[6] S. Kang,et al. Elements of low power design for integrated systems , 2003, Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03..
[7] S. Narendra,et al. Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-/spl mu/m CMOS , 2004, IEEE Journal of Solid-State Circuits.
[8] A. Chandrakasan,et al. A 180-mV subthreshold FFT processor using a minimum energy design methodology , 2005, IEEE Journal of Solid-State Circuits.
[9] Anantha P. Chandrakasan,et al. Minimizing power consumption in digital CMOS circuits , 1995, Proc. IEEE.
[10] Anantha Chandrakasan,et al. Scaling of stack effect and its application for leakage reduction , 2001, ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581).
[11] Andreas G. Andreou,et al. Current-mode subthreshold MOS circuits for analog VLSI neural systems , 1991, IEEE Trans. Neural Networks.
[12] Alice Wang. An ultra-low voltage FFT processor using energy-aware techniques , 2003 .
[13] Massoud Pedram,et al. Low power design methodologies , 1996 .
[14] Kaushik Roy,et al. Ultra-low power DLMS adaptive filter for hearing aid applications , 2001, ISLPED '01.